search for: rshifts

Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de> --- src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp index 58092f4..93f7c2a 100644 ---

def STOREbos { // InstructionEncoding Instruction RPPInst RPPInstMMEMrr &nbsp; field bits<32&gt; Inst = { 0, 0, 0, 1, rs1{2}, rs1{1}, rs1{0}, index{0}, 0, 0, 0, 1, 0, rbase{3}, rbase{2}, rbase{1}, rbase{0}, rbase{4}, roffset{4}, roffset{3}, roffset{2}, roffset{1}, roffset{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; &nbsp; field bits<32&gt; SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

Hi Krzysztof, Today I try it on llvm9.0.0 version. &nbsp; def bos : RPPInstMMEMrr<OPC_STORE, &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; (outs), (ins MGPR:$rs1, SGPR32:$rbase, MGPR:$roffset, uimm2:$rshift), &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; !strconcat(opcodestr, ""), "$rs1,

You are welcome. I changed the pattern, the same old error pop up again, crash in the same place. Type set is empty for each HW mode: possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records). vtInt: &nbsp; (vt:{ *:[Other] }) UNREACHABLE executed at /home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824!

Tested with: MESA_EXTENSION_OVERRIDE=GL_ARB_gpu_shader5 ./shader_runner ../tests/spec/arb_gpu_shader5/execution/built-in-functions/fs-bitfieldReverse.shader_test -> green output, so this should be ok the test was not change though... On 29.05.2014 21:47, Ilia Mirkin wrote: > Can you verify that you tested how the HW handles this, as well as > exactly how you did it (i.e. how did you

Hi, The full trace stack: Type set is empty for each HW mode: possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records). vtInt: (vt:{ *:[Other] }) UNREACHABLE executed at /home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824! [ 85%] Building X86GenEVEX2VEXTables.inc... &nbsp;#0 0x000000000081b9b5

...conds. I also add 2 patches that worked for me. Further info that might help: - The problem seems to be related to silk_burg_modified not reaching the maximum gain, so the actual filter order is 16 rather than 2 (which is what would be expected with a sine wave). - The problem seems to happen when rshifts >= 3 - when pre-scaling the signal to be < 16384 the problem goes away (patch scale_burg_in.diff) - When calculating C0 and rshifts based on a 64 bits correlation instead of using silk_sum_sqr_shift the problem also goes away (patch new_C0_calc.diff) I suspect that for very high prediction g...

And another try for constant folding of Instructions for nvc0. Please Review this! Thanks, Tobias Klausmann Tobias Klausmann (4): nvc0/ir: clear subop when folding constant expressions nvc0/ir: Handle reverse subop for OP_EXTBF when folding constant expressions nvc0/ir: Handle OP_BFIND when folding constant expressions nvc0/ir: Handle OP_POPCNT when folding constant expressions

Can you verify that you tested how the HW handles this, as well as exactly how you did it (i.e. how did you modify the code + piglit test, what the results were, etc) On Thu, May 29, 2014 at 3:43 PM, Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de> wrote: > Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de> > --- >

V2: Handle the instruction right (shift after reverse) Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de> --- src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp

Import "exploiting the new interface in vnc.c" from qemu mainstream. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6337 c046a42c-6fe2-441c-8c8c-71466251a162 Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> --- diff -r 07a126ac0425 console.c --- a/console.c Mon Feb 16 11:39:06 2009 +0000 +++ b/console.c Mon Feb 16 12:07:19 2009 +0000 @@ -1310,6 +1310,9

Hi Marcello, Thanks for the info and the proposed fixes. I'm currently investigating what's going on here before deciding on the best way to fix the problem. Have you been able to figure out why it doesn't work for rshifts >= 3? Cheers, Jean-Marc On 13/06/14 12:28 PM, Marcello Caramma (mcaramma) wrote: > Hi Jean Marc, > > please find attached the audio file (mono 16khz). I shortened it to about > 10 seconds. I also add 2 patches that worked for me. Further info that > might help: > > - T...

Hi, please review the following 4 patches: 1b1cfc6 nvc0/ir: Handle OP_BFIND when folding constant expressions d2d2727 nvc0/ir: Handle OP_POPCNT when folding constant expressions 86a1ee6 nvc0/ir: Handle reverse subop for OP_EXTBF when folding constant expressions 84563bf nvc0/ir: clear subop when folding constant expressions src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 39

...r info that >> might help: >> >> - The problem seems to be related to silk_burg_modified not reaching the >> maximum gain, so the actual filter order is 16 rather than 2 (which is >> what would be expected with a sine wave). >> - The problem seems to happen when rshifts >= 3 >> - when pre-scaling the signal to be < 16384 the problem goes away (patch >> scale_burg_in.diff) >> - When calculating C0 and rshifts based on a 64 bits correlation instead >> of using silk_sum_sqr_shift the problem also goes away (patch >> new_C0_calc.dif...

Yet another try for constant folding of Instructions for nvc0. Please Review this again! (Hopefully the last time ;-) ) Tobias Klausmann (4): nvc0/ir: clear subop when folding constant expressions nvc0/ir: Handle reverse subop for OP_EXTBF when folding constant expressions nvc0/ir: Handle OP_BFIND when folding constant expressions nvc0/ir: Handle OP_POPCNT when folding constant

Hi, Here's llvm-tblgen -print-records message: def LOADbos { // Instruction ABCInst ABCInstMMEMrr field bits<32> Inst = { 0, 0, 0, 0, rs1{2}, rs1{1}, rs1{0}, index{0}, 0, 0, 0, 1, 0, rbase{3}, rbase{2}, rbase{1}, rbase{0}, rbase{4}, roffset{4}, roffset{3}, roffset{2}, roffset{1}, roffset{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

...at worked for me. Further info that > might help: > > - The problem seems to be related to silk_burg_modified not reaching the > maximum gain, so the actual filter order is 16 rather than 2 (which is > what would be expected with a sine wave). > - The problem seems to happen when rshifts >= 3 > - when pre-scaling the signal to be < 16384 the problem goes away (patch > scale_burg_in.diff) > - When calculating C0 and rshifts based on a 64 bits correlation instead > of using silk_sum_sqr_shift the problem also goes away (patch > new_C0_calc.diff) > > I susp...

...; might help: >>> >>> - The problem seems to be related to silk_burg_modified not reaching the >>> maximum gain, so the actual filter order is 16 rather than 2 (which is >>> what would be expected with a sine wave). >>> - The problem seems to happen when rshifts >= 3 >>> - when pre-scaling the signal to be < 16384 the problem goes away (patch >>> scale_burg_in.diff) >>> - When calculating C0 and rshifts based on a 64 bits correlation instead >>> of using silk_sum_sqr_shift the problem also goes away (patch >>...

Hi, Apologies if this is a known issues, but I have found what I believe is a bug in the fixed point implementation of the Silk codec and could not find any mention on this in the archives. The bug can be easily reproduced with the fixed point demo program (./configure ?enable-fixed-point ?disable-float-api && make) using the following command: ./opus_demo voip 16000 1 23000

...; > >>> - The problem seems to be related to silk_burg_modified not reaching > the > >>> maximum gain, so the actual filter order is 16 rather than 2 (which is > >>> what would be expected with a sine wave). > >>> - The problem seems to happen when rshifts >= 3 > >>> - when pre-scaling the signal to be < 16384 the problem goes away > (patch > >>> scale_burg_in.diff) > >>> - When calculating C0 and rshifts based on a 64 bits correlation > instead > >>> of using silk_sum_sqr_shift the problem...