search for: rotl

The attached patch contains: - Cleanups in the DAGCombiner.cpp ROTL/ROTR combine code, primarily helping me to fix 80col violations (benefiting the code as a whole). - Detect sign/zext/any-extended versions of ROTL/ROTR patterns. - Allow custom lowering for ROTL/ROTR (needed in the CellSPU's case for 8-bit rotates, when only 16-bit and 32-bit rotates ar...

..., Register:i64 %R1, t12:1 Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1 Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10 Combining: t11: i64 = Register %R1 Combining: t10: i64 = and t2, t9 Combining: t9: i64 = xor t7, Constant:i64<-1> ... into: t15: i64 = rotl Constant:i64<-2>, t6 Combining: t10: i64 = and t2, t15 Combining: t15: i64 = rotl Constant:i64<-2>, t6 Combining: t14: i64 = Constant<-2> Combining: t6: i64 = sub t4, Constant:i64<1> ... into: t17: i64 = add t4, Constant:i64<-1> Combining: t15: i64 = rotl Constan...

One option may be to prevent the formation of ROTL, if possible, and then generating rol by hand. Marking it as "expand" would likely stop the DAG combiner from creating it. Then you could "preprocess" the selection DAG before the instruction selection and do the pattern matching yourself. -Krzysztof On 11/3/2016 4:24 PM,...

Setting the ISD::ROTL to Expand doesn't work? (via SetOperation) You could also do a Custom hook if that's what you're looking for. On Thu, Nov 3, 2016 at 5:12 PM, Phil Tomson <phil.a.tomson at gmail.com> wrote: > ... or perhaps to rephrase: > > In 3.9 it seems to be doing a smaller combine...

..., Register:i64 %R1, t12:1 Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1 Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10 Combining: t11: i64 = Register %R1 Combining: t10: i64 = and t2, t9 Combining: t9: i64 = xor t7, Constant:i64<-1> ... into: t15: i64 = rotl Constant:i64<-2>, t6 ...to this: Optimized lowered selection DAG: BB#0 'bclr64:entry' SelectionDAG has 13 nodes: t0: ch = EntryToken t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0 t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1 t17: i64 = add t4, Constan...

Hi all, While I test "clang-tests/gcc-4_2-testsuite/src/gcc.c-torture/execute/20020226-1.c", I faced something wrong with "DAGCombiner::MatchRotate" function. This function tries to consume some patterns and generate "ROTL" or "ROTR" dag node as following comments: "DAGCombier::MatchRotate" function in DAGCombiner.cpp Pattern1 // fold (or (shl (*ext x), (*ext y)), // (srl (*ext x), (*ext (sub 32, y)))) -> // (*ext (rotl x, y)) // fold (or (shl (*ext x), (*ext y)), //...

Is there any way of determining whether a file has been successfully downloaded by a user or to put it another way, whether a dowload was interrupted? -- Posted via http://www.ruby-forum.com/.

...clude "rijndael.h" - -void gen_tabs __P((void)); - -/* 3. Basic macros for speeding up generic operations */ - -/* Circular rotate of 32 bit values */ - -#define rotr(x,n) (((x) >> ((int)(n))) | ((x) << (32 - (int)(n)))) -#define rotl(x,n) (((x) << ((int)(n))) | ((x) >> (32 - (int)(n)))) - -/* Invert byte order in a 32 bit variable */ - -#define bswap(x) ((rotl(x, 8) & 0x00ff00ff) | (rotr(x, 8) & 0xff00ff00)) - -/* Extract byte from a 32 bit quantity (little endian notation)...

...LLVM back ends do know about rotate instructions on > targets that have them, though, and the llvm optimizers are pretty > smart about recognizing the usual ways to express rotate with shift/ > and/or, as below. > Look in the DAGCombiner.cpp file to see which patterns it translates into ROTL and ROTR instructions. -bw

On Feb 3, 2009, at 2:35 PMPST, Mike Stump wrote: > On Feb 3, 2009, at 2:28 PM, Kasra wrote: >> I was looking around the LLVM instruction set and I failed to find >> ROL and ROR instructions. Is there any plans on adding these >> instructions to LLVM? > > Not sure what you mean: He's referring to the LLVM IR, I think, and it's true that doesn't have

On 7/2/2018 3:16 PM, Sanjay Patel wrote: > I also agree that the per-element rotate for vectors is what we want for > this intrinsic. > > So I have this so far: > > declare i32 @llvm.catshift.i32(i32 %a, i32 %b, i32 %shift_amount) > declare <2 x i32> @llvm.catshift.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %shift_amount) > > For

...in other languages. It seems wasteful for an optimizer to break apart an intrinsic into its elemental pieces in order for LLVM to put them back together. This was done in our compiler for some time and it cluttered up the interface code. Just curious... what kind of optimizations are done on ISD::ROTL/ROTR? We're able to preform certain InstCombines and other peeps when we see a binary operator. I do not have any experience trying to optimize ISD::ROTL. On Tue, Jul 31, 2012 at 12:17 PM, Eli Friedman <eli.friedman at gmail.com>wrote: > On Tue, Jul 31, 2012 at 8:42 AM, Cameron McIna...

v2: - Fix seeding. - Add a test that nbdkit-random-plugin is producing something which looks at least somewhat random. Rich.

...* this is ‘xoshiro256** 1.0’. + * + * This does _NOT_ generate cryptographically secure random numbers + * (CSPRNG) and so should not be used when cryptography or security is + * required - use gcrypt if you need those. + */ + +struct random_state { + uint64_t s[4]; +}; + +static inline uint64_t +rotl (const uint64_t x, int k) +{ + return (x << k) | (x >> (64 - k)); +} + +/* Returns 64 random bits. Updates the state. */ +uint64_t +xrandom (struct random_state *state) +{ + const uint64_t result_starstar = rotl (state->s[1] * 5, 7) * 9; + const uint64_t t = state->s[1] <&l...

...+ return z ^ (z >> 31); +} + +static inline void +xsrandom (uint64_t seed, struct random_state *state) +{ + state->s[0] = snext (&seed); + state->s[1] = snext (&seed); + state->s[2] = snext (&seed); + state->s[3] = snext (&seed); +} + +static inline uint64_t +rotl (const uint64_t x, int k) +{ + return (x << k) | (x >> (64 - k)); +} + +/* Returns 64 random bits. Updates the state. */ +static inline uint64_t +xrandom (struct random_state *state) +{ + const uint64_t result_starstar = rotl (state->s[1] * 5, 7) * 9; + const uint64_t t = state-&...

On Tue, Jul 31, 2012 at 8:42 AM, Cameron McInally <cameron.mcinally at nyu.edu> wrote: > Andy, > > Here is the left circular shift operator patch. I apologize to the reviewer > in advance. The patch has a good bit of fine detail. Any > comments/criticisms? > > Some caveats... > > 1) This is just the bare minimum needed to make the left circular shift > operator

...at random_state is guaranteed to have at least three non-zero values, which was a documented prerequisite of the seeding. > +/* Returns 64 random bits. Updates the state. */ > +static inline uint64_t > +xrandom (struct random_state *state) > +{ > + const uint64_t result_starstar = rotl (state->s[1] * 5, 7) * 9; > + const uint64_t t = state->s[1] << 17; > + > + state->s[2] ^= state->s[0]; > + state->s[3] ^= state->s[1]; > + state->s[1] ^= state->s[2]; > + state->s[0] ^= state->s[3]; > + > + state->s[2] ^= t; >...

...case ISD::UDIV: + case ISD::SREM: + case ISD::UREM: + case ISD::FADD: + case ISD::FSUB: + case ISD::FMUL: + case ISD::FDIV: + case ISD::FREM: + case ISD::AND: + case ISD::OR: + case ISD::XOR: + case ISD::SHL: + case ISD::SRA: + case ISD::SRL: + case ISD::ROTL: + case ISD::ROTR: + case ISD::CTTZ: + case ISD::CTLZ: + case ISD::CTPOP: + case ISD::SELECT: + case ISD::SELECT_CC: + case ISD::SINT_TO_FP: + case ISD::UINT_TO_FP: + case ISD::FP_TO_SINT: + case ISD::FP_TO_UINT: + case ISD::FNEG: + case ISD::FABS: + case ISD:...

...ons on > > targets that have them, though, and the llvm > optimizers are pretty > > smart about recognizing the usual ways to express > rotate with shift/ > > and/or, as below. > > > Look in the DAGCombiner.cpp file to see which patterns it > translates > into ROTL and ROTR instructions. > > -bw I guess the backends could know about the instructions. But I am not convinced why it is beneficial not to have ROR and ROL instructions within llvm. > Look in the DAGCombiner.cpp file to see which patterns it > translates > into ROTL and ROTR instr...

...ilder.h (working copy) @@ -483,6 +483,7 @@ void visitXor (const User &I) { visitBinary(I, ISD::XOR); } void visitShl (const User &I) { visitShift(I, ISD::SHL); } void visitLShr(const User &I) { visitShift(I, ISD::SRL); } + void visitCShl(const User &I) { visitShift(I, ISD::ROTL); } void visitAShr(const User &I) { visitShift(I, ISD::SRA); } void visitICmp(const User &I); void visitFCmp(const User &I);