search for: rofirrim

Yep, exactly that. We see quite a lot of them, most of them get cleaned up, but not always... Cheers. ________________________________ From: Roger Ferrer Ibáñez <rofirrim at gmail.com> Sent: 16 March 2020 08:53 To: Sjoerd Meijer <Sjoerd.Meijer at arm.com> Cc: LLVM-Dev <llvm-dev at lists.llvm.org>; Sam Parker <Sam.Parker at arm.com> Subject: Re: [llvm-dev] Redundant copies At this point however it doesn't (obviously) look like one (it still...

...c to instruction select a specific variant of the hardwarloop with some implicit predication. Cheers, Sjoerd. ________________________________ From: Simon Moll <Simon.Moll at EMEA.NEC.COM> Sent: 19 May 2020 09:56 To: Sjoerd Meijer <Sjoerd.Meijer at arm.com> Cc: Roger Ferrer Ibáñez <rofirrim at gmail.com>; Eli Friedman <efriedma at quicinc.com>; listmail at philipreames.com <listmail at philipreames.com>; llvm-dev <llvm-dev at lists.llvm.org>; Sander De Smalen <Sander.DeSmalen at arm.com>; hanna.kruppe at gmail.com <hanna.kruppe at gmail.com> Subject: R...

...y changed here. Now, this seems very generic, and doesn't seem to bite the VP intrinsics. Cheers, Sjoerd. ________________________________ From: Simon Moll <Simon.Moll at EMEA.NEC.COM> Sent: 19 May 2020 15:07 To: Sjoerd Meijer <Sjoerd.Meijer at arm.com> Cc: Roger Ferrer Ibáñez <rofirrim at gmail.com>; Eli Friedman <efriedma at quicinc.com>; listmail at philipreames.com <listmail at philipreames.com>; llvm-dev <llvm-dev at lists.llvm.org>; Sander De Smalen <Sander.DeSmalen at arm.com>; hanna.kruppe at gmail.com <hanna.kruppe at gmail.com> Subject: R...

...o preference at all what this intrinsic is, it is not relevant, as long as we can make this explicit. Cheers. ________________________________ From: Simon Moll <Simon.Moll at EMEA.NEC.COM> Sent: 18 May 2020 14:11 To: Sjoerd Meijer <Sjoerd.Meijer at arm.com> Cc: Roger Ferrer Ibáñez <rofirrim at gmail.com>; Eli Friedman <efriedma at quicinc.com>; listmail at philipreames.com <listmail at philipreames.com>; llvm-dev <llvm-dev at lists.llvm.org>; Sander De Smalen <Sander.DeSmalen at arm.com>; hanna.kruppe at gmail.com <hanna.kruppe at gmail.com> Subject: R...

Dear Alex, all, I was looking for fcvt.d.{w,l}{,u} in RISCVInstrInfoD and I'm not sure to understand the current definitions: 138 def FCVT_D_W : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.w"> { 139 let rs2 = 0b00000; 140 } 141 142 def FCVT_D_WU : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.wu"> { 143 let rs2 =

...nts/calculates the active mask. I've just uploaded a new revision for D79100 that implements this. Cheers. ________________________________ From: Simon Moll <Simon.Moll at EMEA.NEC.COM> Sent: 18 May 2020 13:32 To: Sjoerd Meijer <Sjoerd.Meijer at arm.com> Cc: Roger Ferrer Ibáñez <rofirrim at gmail.com>; Eli Friedman <efriedma at quicinc.com>; listmail at philipreames.com <listmail at philipreames.com>; llvm-dev <llvm-dev at lists.llvm.org>; Sander De Smalen <Sander.DeSmalen at arm.com>; hanna.kruppe at gmail.com <hanna.kruppe at gmail.com> Subject: R...

...e %evl parameter is inactivated in this way (VPIntrinsic::canIgnoreVectorLengthParam()). Cheers, Sjoerd. - Simon ________________________________ From: Simon Moll <Simon.Moll at EMEA.NEC.COM><mailto:Simon.Moll at EMEA.NEC.COM> Sent: 06 November 2020 10:07 To: Roger Ferrer Ibáñez <rofirrim at gmail.com><mailto:rofirrim at gmail.com>; Sjoerd Meijer <Sjoerd.Meijer at arm.com><mailto:Sjoerd.Meijer at arm.com> Cc: Renato Golin <rengolin at gmail.com><mailto:rengolin at gmail.com>; Vineet Kumar <vineet.kumar at bsc.es><mailto:vineet.kumar at bsc.e...

...e don't need many cases. And kind of similarly, vscale can be a no-op or do something. Cheers, Sjoerd. ________________________________ From: Simon Moll <Simon.Moll at EMEA.NEC.COM> Sent: 06 November 2020 15:37 To: Sjoerd Meijer <Sjoerd.Meijer at arm.com>; Roger Ferrer Ibáñez <rofirrim at gmail.com> Cc: Renato Golin <rengolin at gmail.com>; Vineet Kumar <vineet.kumar at bsc.es>; LLVM Dev <llvm-dev at lists.llvm.org>; ROGER FERRER IBANEZ <roger.ferrer at bsc.es>; Arai, Masaki <arai.masaki at jp.fujitsu.com> Subject: Re: [llvm-dev] Loop-vectorizer p...

Hi Quentin, > It sounds like you only need the earlyclobber description for the N, N > variant. > In other words, as long as you use different opcodes for widen-op NN and > widen-op WN, you model exactly what you want. > > What am I missing? > we are using different opcodes for widen-op NN and widen-op WN. My understanding is that not setting earlyclobber to the W, N

...like to makes this explicit. In this example, the scalar iteration count 10 iis the number of elements processed by this loop, which is what we want to pass on from the vectoriser to backend passes. Hope this helps. Cheers, Sjoerd. ________________________________ From: Roger Ferrer Ibáñez <rofirrim at gmail.com> Sent: 04 May 2020 21:22 To: Sjoerd Meijer <Sjoerd.Meijer at arm.com> Cc: Eli Friedman <efriedma at quicinc.com>; llvm-dev <llvm-dev at lists.llvm.org>; Sam Parker <Sam.Parker at arm.com> Subject: Re: [llvm-dev] LV: predication Hi Sjoerd, That would be an...

On 11/6/20 8:49 AM, Roger Ferrer Ibáñez wrote: Hi Sjoerd, Trying to remember how everything fits together here, but could get.active.lane.mask not create the %mask of the VP intrinsics? Or in other words, in the vectoriser, who's producing the %mask and %evl that is consumed by the VP intrinsics? I'm not sure what would be the best way here. I think about the Loop Vectorizer. I imagine

Hi Sjoerd, I'm already using RDA in the pass I mentioned and it works great. Thanks Sam! Regarding the root cause, I didn't see anything obviously suboptimal not in the copy coalescing or the register allocation, at least in my previous example. Alternatively we might want to improve what we pass onto RA: i.e. remove the redundant copy earlier. At this point however it doesn't

...evl = call @llvm.vscale(256, %n - %i) ; MVE/SVE/AVX : ; %mask = get.active.lane.mask(%i, %n) ; %evl = call @llvm.vscale(... ,..) Cheers, Sjoerd. ________________________________ From: Simon Moll <Simon.Moll at EMEA.NEC.COM> Sent: 06 November 2020 10:07 To: Roger Ferrer Ibáñez <rofirrim at gmail.com>; Sjoerd Meijer <Sjoerd.Meijer at arm.com> Cc: Renato Golin <rengolin at gmail.com>; Vineet Kumar <vineet.kumar at bsc.es>; LLVM Dev <llvm-dev at lists.llvm.org>; ROGER FERRER IBANEZ <roger.ferrer at bsc.es>; Arai, Masaki <arai.masaki at jp.fujitsu.c...

> The harm comes if the intrinsic ends up with the wrong value, or attached to the wrong loop. The intrinsic is marked as IntrNoDuplicate, so I wasn't worried about it ending up somewhere else. Also, it is a property of a specific loop, a tail-folded vector loop, that holds even after it is transformed I think. I.e. unrolling a vector loop is probably not what you want, but even if you do

Hi, Looking at the language reference, vscale is an integer. This might pose a problem for fractional vscale. Furthermore, I believe that vscale is constant throughout the life of the program; so if RISC-V vscale can vary from instruction to instruction that may also be problematic unless you can just commit to one specific value of vscale. Also, I had a question about your table. Based

...k of the VP intrinsics? Or in other words, in the vectoriser, who's producing the %mask and %evl that is consumed by the VP intrinsics? Cheers, Sjoerd. ________________________________ From: Simon Moll <Simon.Moll at EMEA.NEC.COM> Sent: 05 November 2020 11:07 To: Roger Ferrer Ibáñez <rofirrim at gmail.com>; Sjoerd Meijer <Sjoerd.Meijer at arm.com> Cc: Renato Golin <rengolin at gmail.com>; Vineet Kumar <vineet.kumar at bsc.es>; LLVM Dev <llvm-dev at lists.llvm.org>; ROGER FERRER IBANEZ <roger.ferrer at bsc.es>; Arai, Masaki <arai.masaki at jp.fujitsu.c...

Hi all, On Tue, 7 Apr 2020 at 11:04, Renato Golin via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > On Tue, 7 Apr 2020 at 09:30, Kai Wang via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > > LMUL = 1 LMUL = 2 LMUL = 4 LMUL = 8 > > int64_t | vscale x 1 x i64 | vscale x 2 x i64 | vscale x 4 x i64 | vscale x 8 x i64