Displaying 3 results from an estimated 3 matches for "rflaga".
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rflags
2018 Apr 23
2
pre-RA scheduling/live register analysis optimization (handle move) forcing spill of registers
...0B BB#0: derived from LLVM BB %entry
Live Ins: %FA_ROFF1
16B %vreg0<def> = COPY %FA_ROFF1; FPUaOffsetClass:%vreg0
32B %vreg2<def> = MOVSUTO_A_iSLo 1077936128; FPUaOffsetClass:%vreg2
48B %vreg3<def> = FMUL_A_oo %vreg0, %vreg2, %RFLAGA<imp-def,dead>; FPUaROUTMULRegisterClass:%vreg3 FPUaOffsetClass:%vreg0,%vreg2
64B %vreg4<def> = COPY %vreg3; FPUaOffsetClass:%vreg4 FPUaROUTMULRegisterClass:%vreg3
80B %vreg5<def> = MOVSUTO_A_iSLo 1056964608; FPUaOffsetClass:%vreg5
96B %vreg6<...
2018 Sep 10
3
How to avoid multiple registers definitions in customInserter.
...llowed by HOR).
I've introduced an Pseudo instruction with a custom inserter.
def OR_A_oo : CLPPseudoInst<(ins FPUaOffsetOperand:$OffsetA,FPUaOffsetOperand:$OffsetB),(outs FPUaROUTADDRegisterClass:$FA_ROUTADD),
[], [RFLAGA],
"# OR_A_oo",
[(set FPUaROUTADDRegisterClass:$FA_ROUTADD,(or FPUaOffsetOperand:$OffsetA,FPUaOffsetOperand:$OffsetB))],NoItinerary>...
2018 Apr 12
2
How to specify the RegisterClass of an IMPLICIT_DEF?
...%vreg7<def,tied1> = INSERT_SUBREG %vreg5<tied0>, %vreg4, B_UNIT_PART; FPUabRegisterClass:%vreg7,%vreg5 FPUaOffsetClass:%vreg4
%vreg9<def> = COPY %vreg7; FPUabOffsetClass:%vreg9 FPUabRegisterClass:%vreg7
%vreg8<def> = FMUL_AB_oo %vreg0, %vreg9<kill>, %RFLAGA<imp-def,dead>, %RFLAGB<imp-def,dead>, %RSPA<imp-use>, %RSPB<imp-use>; FPUabROUTMULRegisterClass:%vreg8 FPUabOffsetClass:%vreg0,%vreg9
[http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg]
Dominique Torette
System Architect
Rue des Chasseurs Ardennai...