search for: rev64

...ld like to optimize at the IR level. I'd like to turn an Arm/AArch64 table lookup intrinsic that takes a constant vector mask into a shufflevector instruction: vtbl1(V,mask) ~> shufflevector(V,undef,mask) The reason is that if the mask is {7,6,5,4,3,2,1,0}, then the backend will generate rev64 instructions instead. If the mask comes from a vld1 of a global constant I could fold it to allow the above instruction combining. My question is, does the constant folding of the vld1 seem a good thing to do in the general case, as a standalone transformation, or only when used as a mask for a t...

...// %entry > sub sp, sp, #16 // =16 > str x0, [sp, #8] > ldr x0, [sp, #8] > ld1 { v0.2s }, [x0] > add sp, sp, #16 // =16 > ret > > With global-isel off, there is a rev64 instruction between the ld1 and the add, which fixes up the endianness of the vector. > > Oliver > > From: Oliver Stannard > Sent: 17 November 2017 13:32 > To: 'qcolombet at apple.com <mailto:qcolombet at apple.com>' > Cc: llvm-dev at lists.llvm.org <mailt...

...// %entry > sub sp, sp, #16 // =16 > str x0, [sp, #8] > ldr x0, [sp, #8] > ld1 { v0.2s }, [x0] > add sp, sp, #16 // =16 > ret > > With global-isel off, there is a rev64 instruction between the ld1 and the add, which fixes up the endianness of the vector. > > Oliver > > From: Oliver Stannard > Sent: 17 November 2017 13:32 > To: 'qcolombet at apple.com <mailto:qcolombet at apple.com>' > Cc: llvm-dev at lists.llvm.org <mailt...

To give an update here, we actually are not missing a mapping. The code complains because we are copying around a fp16 into a gpr32 and that shouldn’t be done with a copy (default mapping). I extended the repairing code to issue G_ANYEXT in those cases instead of asserting. However, now, I have to teach instruction select about those ANYEXT otherwise we’ll fallback in that case. But that’s a