Displaying 3 results from an estimated 3 matches for "reg64".
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2013 Mar 21
1
[LLVMdev] Simpler types in TableGen isel patterns
This sounds great! I've been bitten in the past by trying to use a single
class for multiple types.
Would it make sense to extend this to all DAG patterns? If I have an
instruction def:
def ANDN64 : MyInst<(outs Reg64:$d), (ins Reg64:$a, Reg64:$b), "and.64 $d,
$a, $b", [(set Reg64:$d, (and (not (Reg64:$a, Reg64:$b))))]>;
would I now be able to write:
def ANDN64 : MyInst<(outs Reg64:$d), (ins Reg64:$a, Reg64:$b), "and.64 $d,
$a, $b", [(set i64:$d, (and (not (i64:$a, i64:$b))))]>;
?...
2013 Mar 21
0
[LLVMdev] Simpler types in TableGen isel patterns
----- Original Message -----
> From: "Jakob Stoklund Olesen" <stoklund at 2pi.dk>
> To: llvmdev at cs.uiuc.edu, llvmdev at cs.uiuc.edu, llvmdev at cs.uiuc.edu, llvmdev at cs.uiuc.edu
> Sent: Thursday, March 21, 2013 1:26:25 PM
> Subject: [LLVMdev] Simpler types in TableGen isel patterns
>
> Currently, instruction selection patterns are defined like this:
>
2013 Mar 21
9
[LLVMdev] Simpler types in TableGen isel patterns
Currently, instruction selection patterns are defined like this:
def : Pat<(and (not GR32:$src1), GR32:$src2),
(ANDN32rr GR32:$src1, GR32:$src2)>;
def : Pat<(and (not GR64:$src1), GR64:$src2),
(ANDN64rr GR64:$src1, GR64:$src2)>;
TableGen infers the types of $src1 and $src2 from the specified register classes, and that is the only purpose of the register