search for: ret_flag

Author: wyllys Repository: /hg/zfs-crypto/gate Revision: 1b97a96daa581c4f53b4fd8acceb76a27a9fe324 Log message: 6310540 6290437 causes gss_accept_sec_context not to output ret_flags whn no deleg cred; breaks ssh Files: update: usr/src/lib/libgss/g_accept_sec_context.c

....0, but I am getting selection errors for 'callseq_end'. I am aware that the 'ADJCALLSTACKUP' and 'ADJCALLSTACKDOWN' patterns have changed, and have added an additional argument to the TD descriptions for these. There are interactions with 'ISD::CALL' and 'ISD::RET_FLAG', but so far as I can tell I have revised these in the same way as the in-tree targets have adjusted their sources. The error I am seeing is: fatal error: error in backend: Cannot select: 0x15c9bbe00: ch,glue = callseq_end 0x15c9bbd98, TargetConstant:i32<0>, TargetGlobalAddress:i32&lt...

...ster:i64 %vreg0 t16: i32,ch = load<LD1[%ptr](tbaa=<0x10023c9f448>), anyext from i8> t0, t2, undef:i64 t15: v16i8 = BUILD_VECTOR t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16 t11: ch,glue = CopyToReg t0, Register:v16i8 %V2, t15 t12: ch = PPCISD::RET_FLAG t11, Register:v16i8 %V2, t11:1 and the following pattern that I'd like to match: def ScalarLoads { dag Li8 = (i32 (extloadi8 xoaddr:$src)); } def : Pat<(v16i8 (build_vector ScalarLoads.Li8, ScalarLoads.Li8, ScalarLoads.Li8, ScalarLoads.Li8,...

...:i32<65535>             t16: i64 = zero_extend t10           t17: i64 = ctlz t16         t22: i64 = add t17, Constant:i64<-32>       t20: i32 = truncate t22     t15: i32 = add t20, Constant:i32<-16>   t7: ch,glue = CopyToReg t0, Register:i32 $r2l, t15   t8: ch = SystemZISD::RET_FLAG t7, Register:i32 $r2l, t7:1 It seems that SelectionDAG::computeKnownBits() has a case for ISD::CTLZ, and it seems to figure out that the high bits of t17 are zero, as expected. t17 is guaranteed to have a value between 48 and 64, so there could not be any overflow here, even though I am not sur...

...g selection errors for 'callseq_end'. I am aware that the > 'ADJCALLSTACKUP' and 'ADJCALLSTACKDOWN' patterns have changed, and have > added an additional argument to the TD descriptions for these. > > There are interactions with 'ISD::CALL' and 'ISD::RET_FLAG', but so far as > I > can tell I have revised these in the same way as the in-tree targets have > adjusted their sources. > > The error I am seeing is: > > fatal error: error in backend: Cannot select: 0x15c9bbe00: ch,glue = > callseq_end 0x15c9bbd98, TargetConstant:i3...

...ke the call SDNodes are: --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -117,7 +117,7 @@ def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, SDNPVariadic]>; def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, - [SDNPHasChain, SDNPOptInGlue]>; + [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, [SDNPInGlue]>; 2. Fast isel...

...try' SelectionDAG has 9 nodes: t0: ch = EntryToken t3: i64 = Constant<0> t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0 t5: v4i32,ch = load<LD16[%0](tbaa=<0x10038f18a98>)> t0, t2, undef:i64 t7: ch,glue = CopyToReg t0, Register:v4i32 %V2, t5 t8: ch = PPCISD::RET_FLAG t7, Register:v4i32 %V2, t7:1 What I would like to do is emit efficient code for cases where the parameter pointer has the same alignment requirements as the load and emit the conservative but less efficient code in other cases. Nemanja -------------- next part -------------- An HTML attachment wa...

...s, your add becomes a MVrr instruction. This is likely the problem. > Do you know how to debug this, or do you want me to give you basic directions? I had a look at the matcher table and it looks as follows: /*4309*/ /*Scope*/ 12, /*->4322*/ /*4310*/ OPC_CheckOpcode, TARGET_VAL(MBPISD::RET_FLAG), /*4313*/ OPC_RecordNode, // #0 = 'retflag' chained node /*4314*/ OPC_CaptureGlueInput, /*4315*/ OPC_EmitMergeInputChains1_0, /*4316*/ OPC_MorphNodeTo, TARGET_VAL(MyTarget::RETL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic0, 0/*#VTs*/, 0/*#Ops*/, /...

...t37, TargetGlobalAddress:i16<float (float, float, float, float)* @fdivfaddfmul_a> 0, t37:1 t41: ch,glue = callseq_end t39, TargetConstant:i16<4>, TargetConstant:i16<0>, t39:1 t42: f32,ch,glue = CLPISD::COPY_TO_CALLER_A t41, FrameIndex:i16<0>, t41:1 t43: ch = CLPISD::RET_FLAG t42:1 This node is first 'combined' into node t51 (bitcast of ConstantFP f32 to Constant i32). Combining: t13: ch = store<Volatile ST4[@x1](tbaa=<0x3dbe418>)> t8, ConstantFP:f32<1.000000e+00>, GlobalAddress:i16<float* @x1> 0, undef:i16 ... into: t51: ch = store<...

...des: > t0: ch = EntryToken > t3: i64 = Constant<0> > t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0 > t5: v4i32,ch = load<LD16[%0](tbaa=<0x10038f18a98>)> t0, t2, undef:i64 > t7: ch,glue = CopyToReg t0, Register:v4i32 %V2, t5 > t8: ch = PPCISD::RET_FLAG t7, Register:v4i32 %V2, t7:1 > > What I would like to do is emit efficient code for cases where the parameter pointer has the same alignment requirements as the load and emit the conservative but less efficient code in other cases. Do you actually need to know the original type for this?...

...> (float, float, float, float)* @fdivfaddfmul_a> 0, t37:1 > > t41: ch,glue = callseq_end t39, TargetConstant:i16<4>, > TargetConstant:i16<0>, t39:1 > > t42: f32,ch,glue = CLPISD::COPY_TO_CALLER_A t41, FrameIndex:i16<0>, t41:1 > >   t43: ch = CLPISD::RET_FLAG t42:1 > > This node is first ‘combined’ into node t51 (bitcast of ConstantFP f32 > to Constant i32). > > Combining: t13: ch = store<Volatile ST4[@x1](tbaa=<0x3dbe418>)> t8, > ConstantFP:f32<1.000000e+00>, GlobalAddress:i16<float* @x1> 0, undef:i16 >...

Hi, Is there a kind of scope mechanism in the instruction lowering pattern language in order to control where instructions are inserted or how they are later reordered during the SelectionDiag linearization? I know the glue chain that stick instructions together. But such mechanism in not provided in instruction lowering pattern. I'm facing many situations where some patterns are lowered into

...t; [ORD=8] 0x3ea4e20: <multiple use> 0x3ea44d8: i32 = Constant<0> 0x3ea4f28: ch,glue = CopyToReg 0x3ea4d18, 0x3ea4e20, 0x3ea44d8 [ORD=9] 0x3ea4f28: <multiple use> 0x3ea4e20: <multiple use> 0x3ea4f28: <multiple use> 0x3ea5030: ch = EsenciaISD::RET_FLAG 0x3ea4f28, 0x3ea4e20, 0x3ea4f28:1 [ORD=9] Optimized lowered selection DAG: BB#0 'main:entry' SelectionDAG has 14 nodes: 0x3e7e2f0: ch = EntryToken 0x3ea45e0: i32 = undef 0x3e7e2f0: <multiple use> 0x3ea43d0: i32 = FrameIndex<1> 0x3ea45e0: <multiple use>...

...0x26757e8: i32 = extract_vector_elt 0x2675da8, 0x26721e0 [ORD=9] [ID=-3] 0x26755d8: ch,glue = CopyToReg 0x2671fd0, 0x2672600, 0x26757e8 [ORD=13] [ID=-3] 0x26755d8: <multiple use> 0x2672600: <multiple use> 0x26755d8: <multiple use> 0x26750b0: ch = EsenciaISD::RET_FLAG 0x26755d8, 0x2672600, 0x26755d8:1 [ORD=13] [ID=-3] -- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160322/72f7179f/attachment.html>

...float, float, float, float)* @fdivfaddfmul_a> 0, t37:1 > > t41: ch,glue = callseq_end t39, TargetConstant:i16<4>, > TargetConstant:i16<0>, t39:1 > > t42: f32,ch,glue = CLPISD::COPY_TO_CALLER_A t41, FrameIndex:i16<0>, > t41:1 > >   t43: ch = CLPISD::RET_FLAG t42:1 > > This node is first ‘combined’ into node t51 (bitcast of ConstantFP f32 > to Constant i32). > > Combining: t13: ch = store<Volatile ST4[@x1](tbaa=<0x3dbe418>)> t8, > ConstantFP:f32<1.000000e+00>, GlobalAddress:i16<float* @x1> 0, > undef:i16...

...r.argc.addr)> t9, t2, FrameIndex:i64<1>, undef:i64 t4: i64,ch = CopyFromReg t0, Register:i64 %1 t13: ch = store<(store 8 into %ir.argv.addr)> t11, t4, FrameIndex:i64<2>, undef:i64 t16: ch,glue = CopyToReg t13, Register:i32 $eax, Constant:i32<0> t17: ch = X86ISD::RET_FLAG t16, TargetConstant:i32<0>, Register:i32 $eax, t16:1 where the t16 line corresponds to what you've seen on SPARC. Cheers. Tim.

...FTOI: return "SPISD::FTOI"; ! case SPISD::ITOF: return "SPISD::ITOF"; ! case SPISD::FTOX: return "SPISD::FTOX"; ! case SPISD::XTOF: return "SPISD::XTOF"; ! case SPISD::CALL: return "SPISD::CALL"; ! case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG"; ! case SPISD::FLUSHW: return "SPISD::FLUSHW"; ! case SPISD::TLS_ADD: return "SPISD::TLS_ADD"; ! case SPISD::TLS_LD: return "SPISD::TLS_LD&quot...

Hi Mark, >> Sounds like your load / store address selection routine isn't working >> like what you expected. >> > > Thanks for the reply. Unfortunately, this doesn't seem to be the problem. do you handle truncating stores and extending loads? Ciao, Duncan.

...be correct, but a FrameIndex of 0 as been introduced : Optimized legalized selection DAG: BB#0 'storeloadi32:' SelectionDAG has 6 nodes: t0: ch = EntryToken t5: ch = store<Volatile ST4[%ptr]> t0, Constant:i32<12>, FrameIndex:i16<0>, undef:i16 t6: ch = CLPISD::RET_FLAG t5 ISEL: Starting pattern match on root node: t5: ch = store<Volatile ST4[%ptr]> t0, Constant:i32<12>, FrameIndex:i16<0>, undef:i16 The lowering correctly catches the store and morphs to right MOVSUTO_A_iSLr MC instruction: Initial Opcode index to 331 Skipped scope entry (d...

...F"; - case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho"; - case PPCISD::MTCTR: return "PPCISD::MTCTR"; - case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho"; - case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF"; - case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; - case PPCISD::MFCR: return "PPCISD::MFCR"; - case PPCISD::VCMP: return "PPCISD::VCMP"; - case PPCISD::VCMPo: return "PPCISD::VCMPo"; - case PPCISD::LBRX: return "PPCISD::LBRX";...