search for: regmask

Displaying 20 results from an estimated 197 matches for "regmask".

2016 May 27
3
Updating RegMask inline
...i <mehdi.amini at apple.com> wrote: > > > On May 27, 2016, at 11:49 AM, vivek pandya <vivekvpandya at gmail.com> > wrote: > > > > Hello Mentors, > > > > I have completed writing simple register mask calculator pass, an > immutable pass that stores RegMasks and provides API to query them, and a > target specific pass for X86 target which currently iterates through all MI > in given MF and if a call instruction is found then it quires for RegMask > to Immutable pass and prints which registers are clobbered and preserved as > per actual reg...
2016 May 27
2
Updating RegMask inline
Hello Mentors, I have completed writing simple register mask calculator pass, an immutable pass that stores RegMasks and provides API to query them, and a target specific pass for X86 target which currently iterates through all MI in given MF and if a call instruction is found then it quires for RegMask to Immutable pass and prints which registers are clobbered and preserved as per actual register allocation for...
2016 May 28
0
Updating RegMask inline
...rote: > >> >> > On May 27, 2016, at 11:49 AM, vivek pandya <vivekvpandya at gmail.com> >> wrote: >> > >> > Hello Mentors, >> > >> > I have completed writing simple register mask calculator pass, an >> immutable pass that stores RegMasks and provides API to query them, and a >> target specific pass for X86 target which currently iterates through all MI >> in given MF and if a call instruction is found then it quires for RegMask >> to Immutable pass and prints which registers are clobbered and preserved as >&gt...
2016 May 28
1
Updating RegMask inline
...te: >>> >>> > On May 27, 2016, at 11:49 AM, vivek pandya <vivekvpandya at gmail.com> wrote: >>> > >>> > Hello Mentors, >>> > >>> > I have completed writing simple register mask calculator pass, an immutable pass that stores RegMasks and provides API to query them, and a target specific pass for X86 target which currently iterates through all MI in given MF and if a call instruction is found then it quires for RegMask to Immutable pass and prints which registers are clobbered and preserved as per actual register allocation for...
2016 May 28
3
Updating RegMask inline
...gt; wrote: > > > On May 27, 2016, at 11:49 AM, vivek pandya <vivekvpandya at gmail.com <mailto:vivekvpandya at gmail.com>> wrote: > > > > Hello Mentors, > > > > I have completed writing simple register mask calculator pass, an immutable pass that stores RegMasks and provides API to query them, and a target specific pass for X86 target which currently iterates through all MI in given MF and if a call instruction is found then it quires for RegMask to Immutable pass and prints which registers are clobbered and preserved as per actual register allocation for...
2016 May 28
0
Updating RegMask inline
...> > On May 27, 2016, at 11:49 AM, vivek pandya <vivekvpandya at gmail.com> >>> wrote: >>> > >>> > Hello Mentors, >>> > >>> > I have completed writing simple register mask calculator pass, an >>> immutable pass that stores RegMasks and provides API to query them, and a >>> target specific pass for X86 target which currently iterates through all MI >>> in given MF and if a call instruction is found then it quires for RegMask >>> to Immutable pass and prints which registers are clobbered and preserve...
2016 May 27
0
Updating RegMask inline
> On May 27, 2016, at 11:49 AM, vivek pandya <vivekvpandya at gmail.com> wrote: > > Hello Mentors, > > I have completed writing simple register mask calculator pass, an immutable pass that stores RegMasks and provides API to query them, and a target specific pass for X86 target which currently iterates through all MI in given MF and if a call instruction is found then it quires for RegMask to Immutable pass and prints which registers are clobbered and preserved as per actual register allocation for...
2016 May 28
1
Updating RegMask inline
...gt; On May 27, 2016, at 11:49 AM, vivek pandya <vivekvpandya at gmail.com> wrote: >>>>> > >>>>> > Hello Mentors, >>>>> > >>>>> > I have completed writing simple register mask calculator pass, an immutable pass that stores RegMasks and provides API to query them, and a target specific pass for X86 target which currently iterates through all MI in given MF and if a call instruction is found then it quires for RegMask to Immutable pass and prints which registers are clobbered and preserved as per actual register allocation for...
2016 May 28
2
Updating RegMask inline
static void setXXX(MachineInstr &MI, ...) { for (MachineOperand &MO : MI.operands()) { if (MO.isRegMask()) MO.setRegMask(...); } } > On May 27, 2016, at 7:02 PM, vivek pandya via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > > On Sat, May 28, 2016 at 7:29 AM, Matthias Braun <matze at braunis.de <mailto:matze at braunis.de>> wrote: > >> On May 27...
2016 May 28
0
Updating RegMask inline
On Sat, May 28, 2016 at 7:33 AM, Matthias Braun <matze at braunis.de> wrote: > static void setXXX(MachineInstr &MI, ...) { > for (MachineOperand &MO : MI.operands()) { > if (MO.isRegMask()) > MO.setRegMask(...); > } > } > > Ok this is what Mehdi Amini suggested. I will do that, but just to note this will add method to MO so this change is not completely contained in IPRA files. Vivek > On May 27, 2016, at 7:02 PM, vivek pandya via llvm-dev < > llvm-dev at l...
2016 Jul 15
4
RFC: To add __attribute__((regmask("preserve/clobbered list here"))) in clang
...in current module. IPRA's scope is limited to a module so for such externally defined function it uses default calling convention but here as the function is written in assembly user can provide exact register usage detials. So we dicided to mark declration of such function with __attribute__((regmask("clobbered list here"))) so LLVM can construct regmask out of it and use it with IPRA to improve register allocation. For this purpose I added support for this attribute in clang and clang codegen this attribute as target dependent attribute and add to declaration. Then IPRA constructs r...
2017 Jan 12
2
RFC: Dynamically Allocated "Callee Saved Registers" Lists
...ation – No implementation // Assume that the value is returned in EAX and the arguments are passed in EAX, ECX, EDX, ESI, EDI. int __regcall callee (int a, int b, int c, int d, int e); // implemented in a different module void caller() { … x = callee(1,2,3,4,5); … } What will be RegMask using IPRA register usage collector? Callee Saved Registers (from the static register mask) minus RAX. What should really be the RegMask? Callee Saved Registers (from the static register mask) minus RAX, ESI and EDI (and their sub registers). Do you think that I should fix IPRA collector? Even af...
2016 Jun 19
2
[GSoC 2016] [Weekly Status] Interprocedural Register Allocation
Dear Community, Please find summary of work done during this week as follow: Implementation: ============ During this week we have identified a bug in IPRA due to not considering RegMask of function calls in given machine function. The same bug on AArch64 has been reported by Chad Rosier and more detailed description can be found at https://llvm.org/bugs/show_bug.cgi?id=28144 . To fix this bug RegMask calculation have been modified to consider RegMask of function ca...
2017 Jan 12
2
RFC: Dynamically Allocated "Callee Saved Registers" Lists
Hi Mehdi, I think that the subject of the RFC is misleading. The true problem that we are trying to solve is to remove returned/passed arguments from the regmask (According to the calling convention). IPRA and CC updated RegMask can’t use the same mechanism because they contradict each other. I think that the following analog will help to explain why I think that a reuse is redundant: Let’s assume two different functions (FuncA and FuncB) need to allocate...
2013 Nov 22
0
[LLVMdev] PrologEpilogProblems;
...P, 44; mem:ST4[FixedStack0] ST %S1<kill>, %SP, 40; mem:ST4[FixedStack1] ST %S0<kill>, %SP, 36; mem:ST4[FixedStack2] PROLOG_LABEL <MCSym=_tmp1> %S0<def> = LD %SP, 48; mem:LD4[FixedStack-1](align=8) ST %S0, %SP, 0; mem:ST4[FixedStack-4](align=8) JSUB <ga:@extract_l>, <regmask>, %LR<imp-def>, %SP<imp-def>, %V0<imp-def> %V1<def> = ADDI %ZERO, 1 ST %V0<kill>, %SP, 0; mem:ST4[FixedStack-5](align=8) ST %V1<kill>, %SP, 4; mem:ST4[FixedStack-6] JSUB <ga:@shr>, <regmask>, %LR<imp-def>, %SP<imp-def>, %V0<imp-def&g...
2016 Jun 15
2
[GSoC 2016] [Weekly Status] Interprocedural Register Allocation
...qcolombet at apple.com> wrote: > Hi Vivek, > > How much of the slow down on runtime comes from the different layout of > the function in the asm file? (I.e., because of the dummy scc pass.) > > Hello Quentin, Please do not consider previous results as there was a major bug in RegMask calculation due to not considering RegMasks of callee in MF body while calculating register usage information, that has been fixed now ( as discussed with Matthias Braun and Mehdi Amini ) and after this bugfix I have run test-suite with and without IPRA. Yes there is runtime slow down for some tes...
2017 Jan 12
2
RFC: Dynamically Allocated "Callee Saved Registers" Lists
Hi Mehdi, It is true that both IPRA and the proposed mechanism save RegMasks. So you might say that the data structure in the immutable pass should be reused, but this is the only similarity. Even this similarity is not exactly true. I save register masks that doesn’t use passed/returned arguments while IPRA saves register masks for modified registers. So how can they...
2016 May 28
2
[GSoC 2016] [Weekly Status] Interprocedural Register Allocation
...related stuffs from the mentors and also due to patch for CodeGen reordering was provided by dear mentor Mehdi Amini. So I conclude the work done during this week as follows: Implementation : ============ Following passes have been implemented during this week: An immutable pass to store competed RegMask, a machine function pass that iterates through each registers and check if it is used or not and based on that details create a RegMask and a target specific machine function pass that uses the RegMask created by second pass and propagates information by updating call instructions RegMask. To upda...
2017 Jan 11
2
RFC: Dynamically Allocated "Callee Saved Registers" Lists
...In my case, this is a functional issue. The analysis must run in order to be compatible with other compilers. 2. IPRA passes are not enabled by default and when they are enabled many tests fail due to various reasons (mainly because the CallGraph bottom up approach). 3. The manipulated RegMasks generated using RegUsageInfoCollector are very different than the manipulated RegMasks that I need. It will be an abuse to change the current pass implementation. So new pass is required. 4. When dumping the MIR after running IPRA passes, assertion is raised because the RegMask name is unkno...
2016 Jun 20
2
[GSoC 2016] [Weekly Status] Interprocedural Register Allocation
...eBasicBlock &MBB : MF) { for (MachineInstr &MI : MBB) { if (!MI.isCall()) continue; DEBUG(dbgs() << "Call Instruction Before Register Usage Info Propagation : \n"); DEBUG(dbgs() << MI << "\n"); auto UpdateRegMask = [&](const Function *F) { const auto *RegMask = PRUI->getRegUsageInfo(F); if (!RegMask) return; setRegMask(MI, &(*RegMask)[0]); Changed = true; }; MachineOperand &Operand = MI.getOperand(0); if (Operand.isGlobal())...