search for: registeroperand

...return false; }]>; foreach RegId = 0-31 in def Mask#RegId : MipsReg<0, "Mask"#RegId>, DwarfRegNum<[!add(RegId, 10)]>; def VK128: RegisterClass<"Connex", [v128i1], 32, (sequence "Mask%u", 0, 31)>; def VK128Opnd : RegisterOperand<VK128> { let ParserMatchClass = MSA128AsmOperand; } class LD_INDIRECT_DESC_BASE2<string instr_asm, ValueType TyNode, RegisterOperand ROWD, RegisterOperand ROWSI = ROWD, RegisterOperand ROW...

...} def vx256xmem : X86VMemOperand<MSA128D, "printi256mem">; def vectoraddr : ComplexPattern<iPTR, 5, "selectVectorAddr", [],[SDNPWantParent]>; class LD_INDIRECT_DESC_BASE2<string instr_asm, RegisterOperand ROWD, RegisterOperand ROWSP = ROWD, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs ROWD:$wd, VK128Opnd:$wdm); dag InOperandList = (ins ROWSP:$wsp, VK128Opnd:$wsm, vx256xmem:$wsi);...

...def vx256xmem : X86VMemOperand<MSA128D, "printi256mem">; > > def vectoraddr : ComplexPattern<iPTR, 5, "selectVectorAddr", [],[SDNPWantParent]>; > > class LD_INDIRECT_DESC_BASE2<string instr_asm, > RegisterOperand ROWD, > RegisterOperand ROWSP = ROWD, > InstrItinClass itin = NoItinerary> { > dag OutOperandList = (outs ROWD:$wd, VK128Opnd:$wdm); > dag InOperandList = (ins ROWSP:$wsp, VK128Opnd:$wsm, vx25...

Hi Alex, I don’t know too much about recent MIPS, but have recently been doing something similar for the new ARM SVE architecture, so hopefully this will get you closer to what you need: If you’re looking where I think you are (lib/Target/X86/X86InstrAVX512.td), ‘GatherNode’ is a template argument, not a definition. It allows a PatFrag be passed into the avx512_gather multiclass definition.

...m Mips' MSA SIMD extensions.) Could you please tell me what's the right way to do it? Here, the load class has $addrsrc which is a relative address with base a certain register and offset: class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, ValueType TyNode, RegisterOperand ROWD, Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs ROWD:$wd); dag InOperandList = (ins MemOpnd:$addrsrc); string AsmString = !strconcat("mov $wd, ($addrsrc)"); list<dag> Patt...

...we were rejecting them precisely because the patterns now contain value types instead of register classes (FastISelEmitter.cpp, lines 253ff.): // For now, the only other thing we accept is register operands. const CodeGenRegisterClass *RC = 0; if (OpLeafRec->isSubClassOf("RegisterOperand")) OpLeafRec = OpLeafRec->getValueAsDef("RegClass"); if (OpLeafRec->isSubClassOf("RegisterClass")) RC = &Target.getRegisterClass(OpLeafRec); else if (OpLeafRec->isSubClassOf("Register")) RC = Target.getRegBank().get...

Hi Sean, Just to give the GlobalISel perspective on this, GlobalISel supports the declaration of a zero register in the register class like so: def GPR32z : RegisterOperand<GPR32> { let GIZeroRegister = WZR; } With that definition, the tablegen-erated ISel code will try to replace will try to replace 'G_CONSTANT s32 0' with WZR whenever the operand is specified as GPR32z. > On 21 Dec 2017, at 21:22, Sean Silva via llvm-dev <llvm-dev at lists.l...

...2018 at 8:28 AM, Daniel Sanders <daniel_l_sanders at apple.com> wrote: > Hi Sean, > > Just to give the GlobalISel perspective on this, Thanks for chiming in! > GlobalISel supports the declaration of a zero register in the register > class like so: > def GPR32z : RegisterOperand<GPR32> { > let GIZeroRegister = WZR; > } > With that definition, the tablegen-erated ISel code will try to replace > will try to replace 'G_CONSTANT s32 0' with WZR whenever the operand is > specified as GPR32z. > Is this method extensible to the...

Hello. I read on page 4 of http://www.cs.fsu.edu/~whalley/cda5155/chap4.pdf that gather and scatter operations exist for Mips, named LVI and SVI, respectively. Did anyone think of implementing in the LLVM Mips back end (part of the MSA vector instructions) gather and scatter operations? If so, can you share with me the TableGen spec? (I tried to start from LD_DESC_BASE, but it

...r/lib/Target/Mips/MipsMSAInstrInfo.td, look for "def ST_D", etc. Note however that my vector unit has a separate memory space. This is why I defined the vector store like: class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode, ValueType TyNode, RegisterOperand ROWD, Operand MemOpnd = uimm4_ptr, ImmLeaf Addr = immLeafAlex, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs); dag InOperandList = (ins ROWD:$wd, MemOpnd:$addrdst); string AsmString = !strconcat("LS[$addrdst] = $...

...isely because the patterns now > contain value types instead of register classes (FastISelEmitter.cpp, > lines 253ff.): > > // For now, the only other thing we accept is register operands. > const CodeGenRegisterClass *RC = 0; > if (OpLeafRec->isSubClassOf("RegisterOperand")) > OpLeafRec = OpLeafRec->getValueAsDef("RegClass"); > if (OpLeafRec->isSubClassOf("RegisterClass")) > RC = &Target.getRegisterClass(OpLeafRec); > else if (OpLeafRec->isSubClassOf("Register")) > RC = Tar...

For example, given a multiclass for ADD 32 bit that might produce something like: ADD32_REG_REG_REG (operands are all registers for a 32 bit add) ADD32_REG_IMM_REG (srcA is a register, srcB is an immediate and dst is a register) ADD32_REG_IMM_MEM (srcA is a register, srcB is an immediate and dst is a memory address) What I'd like to do is replace an operand, for example, change srcA from a

...t apple.com <mailto:daniel_l_sanders at apple.com>> wrote: > Hi Sean, > > Just to give the GlobalISel perspective on this, > > Thanks for chiming in! > > GlobalISel supports the declaration of a zero register in the register class like so: > def GPR32z : RegisterOperand<GPR32> { > let GIZeroRegister = WZR; > } > With that definition, the tablegen-erated ISel code will try to replace will try to replace 'G_CONSTANT s32 0' with WZR whenever the operand is specified as GPR32z. > > > Is this method extensible to the...

...ter/lib/Target/Mips/MipsMSAInstrInfo.td, look for "def ST_D", etc. Note however that my vector unit has a separate memory space. This is why I defined the vector store like: class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode, ValueType TyNode, RegisterOperand ROWD, Operand MemOpnd = uimm4_ptr, ImmLeaf Addr = immLeafAlex, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs); dag InOperandList = (ins ROWD:$wd, MemOpnd:$addrdst); string AsmString = !strconcat("LS[$addrdst] = $...

I looked around the codebase and didn't see anything that obviously looked like the natural place to turn constant zero immediates into zero-registers (i.e. registers that always return zero when read). Right now we are expanding them in ISelLowering::LowerOperation but that seems too early. The specific issue I'm hitting is that we have a register that reads as -1 and so when we replace

...Could you please tell me what's the right way to do it? > > > Here, the load class has $addrsrc which is a relative address with base a > certain > register and offset: > class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, > ValueType TyNode, RegisterOperand ROWD, > Operand MemOpnd = mem_msa, > ComplexPattern Addr = addrimm10, > InstrItinClass itin = NoItinerary> { > dag OutOperandList = (outs ROWD:$wd); > dag InOperandList = (ins MemOpnd:$addrsrc); > string AsmString = !strconcat("mov $wd, ($addrsrc)&q...

...tions for every > permutation of register and immediate operands, although I realize this is > what most targets seem to do. Then you can simply replace the operand of > the instruction rather than having to figure out the new opcode you need to > use. What AMDGPU does is define various RegisterOperands with custom types > that are allowed by the verifier to contain immediates. The same principle > should also work for mem operands. You could also try to define an > InstrMapping to get the other versions of the opcode. > > -Matt > -------------- next part -------------- An HTML...

...> > contain value types instead of register classes (FastISelEmitter.cpp, > > lines 253ff.): > > > > // For now, the only other thing we accept is register operands. > > const CodeGenRegisterClass *RC = 0; > > if (OpLeafRec->isSubClassOf("RegisterOperand")) > > OpLeafRec = OpLeafRec->getValueAsDef("RegClass"); > > if (OpLeafRec->isSubClassOf("RegisterClass")) > > RC = &Target.getRegisterClass(OpLeafRec); > > else if (OpLeafRec->isSubClassOf("Register"))...

...ought about how the HwMode/variable-sized register class proposal might interact with register AsmNames at all? This old patch that never landed <http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20141201/246835.html> is also I think related. Backends like Mips and PPC end up defining RegisterOperand with a ParserMatchClass (in the Mips case, this specified the 'parseAnyRegister' ParserMethod. Adding a ParserMatchClass field to RegisterClass would be a minor simplification. Best, Alex

Hello. Sometimes the constraints imposed on an instruction's encoding are too complex to be described in tablegen alone. In such cases a custom decoder method is implemented. This makes sense when the decoding itself is very complex, but it is wasteful to do it only when checking additional constraints. This is because: 1. a custom decoder method has to decode operands, set opcodes, etc. -