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Hi, I've run into an issue with the RegisterBankEmitter on the AMDGPU backend. AMDGPU has a register class: VS_32, which is non-allocatable and contains registers from both defined register banks (SGPRRegBank and VGPRRegBank). The RegisterBankEmitter is adding this class to the CoverageData array for both register classes, because it contains su...

...er. > On 10 May 2017, at 16:58, Quentin Colombet <qcolombet at apple.com> wrote: > > Hi Tom, > >> On May 10, 2017, at 7:15 AM, Tom Stellard via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> >> Hi, >> >> I've run into an issue with the RegisterBankEmitter on the AMDGPU backend. >> AMDGPU has a register class: VS_32, which is non-allocatable and contains >> registers from both defined register banks (SGPRRegBank and VGPRRegBank). >> >> The RegisterBankEmitter is adding this class to the CoverageData array >> for...

...er indices but that's likely to be quite painful. I'll have a think and see if I can come up with something nicer. > > I haven't been able to come up with a better answer for this, just an alternate choice as to where the complexity is. If we were to change the second argument of RegisterBank<> to a dag then we could provide a choice of following the class-with-subregs rule or not. This would allow us to prevent it from following the subreg indices into the wrong classes but it would also make it harder to define the register banks. > I'm a little confused about what the...

...broad vector support is one on the reason we target O0, i.e., the vectorizer doesn’t run and we are less likely to hit the missing implementation. ** RegBankSelect ** - Core logic is present, no optimizations yet, or more accurately, the greedy mode is still pretty silly. - TableGen support for RegisterBanks description. * What’s Left * - TableGen the instruction mapping from the existing SDISel patterns. - Improve the optimization heuristic. ** InstructionSelect ** - Core logic present. - TableGen support for simple SDISel patterns (i.e., GISel reuses SDISel patterns) * What’s Left * - Teach T...

Hi LLVM developers, Don't be quiet :) we need your suggestions for supporting custom CCState, CCAssignFn in D41700. And also RegisterBank in D41653. because it needs to consider about how to support variable-sized register classes concept implemented in D24631. And I think you might have same question when porting to GlobalISel for your Targets, so please give us some directions, thanks a lot! 在 2018年01月04日 06:00, Alex Bradbury...

...anches and gcc-8 trunk. 非常感谢！龙芯战士们临近春节还奋战在Mozilla、Linux Kernel、GCC、Binutils，但依然抽出休息时间审核我的工作，非常感激！ 在 2018年01月13日 18:58, Leslie Zhai 写道: > Hi LLVM developers, > > Don't be quiet :) we need your suggestions for supporting custom > CCState, CCAssignFn in D41700. > > And also RegisterBank in D41653. because it needs to consider about > how to support variable-sized register classes concept implemented in > D24631. > > And I think you might have same question when porting to GlobalISel > for your Targets, so please give us some directions, thanks a lot! > > &g...

This question came about through reviewing work from Leslie Zhai on GlobalISel support for RISC-V, which also motivated me to revisit code which I've always felt was a bit clunky. Calling convention lowering in LLVM is typically handled by functions conforming to the CCAssignFn typedef: typedef bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT,

Hi Quentin, thank you for the reply! I have a couple more questions that came up when I tried to implement this today. I hope you can help me out with this again! Am 09.03.20 um 23:31 schrieb Quentin Colombet: > I would expect that you could create a register class and register > bank for the special register. That way you have something to map to > when you do register bank select.

Hi all, Over the past few months we’ve been doing work on the foundations for the next stages of GlobalISel development. In terms of changes from this time last year, the IR translator, the legalizer, and instruction selector have seen moderate to major changes. The most significant of these was the change to the legalizer API, allowing targets to use predicates to express legality, which gives