search for: registerbanks

...egisterBankEmitter is adding this class to the CoverageData array for both register classes, because it contains sub-registers of one of the classes explicitly added to the RegisterBank, for example: Added VS_32(explicit (VS_32) VReg_64 class-with-subregs: VReg_64) This is a problem, because both RegisterBanks think they cover VS_32, even though neither of them actually do. What exactly is the best way to fix this? It seems like we need some additional checks in the RegisterBankEmitter to fix this, but it's not clear to me what we should be checking for. Thanks, Tom

...eData array >> for both register classes, because it contains sub-registers of one >> of the classes explicitly added to the RegisterBank, for example: >> >> Added VS_32(explicit (VS_32) VReg_64 class-with-subregs: VReg_64) >> >> This is a problem, because both RegisterBanks think they cover >> VS_32, even though neither of them actually do. > > I agree this is a bug in the emitter. It should only add the subclasses of VS_32 that projects to V (resp. S) for the given subregs. > > I let Daniel comment further. > > Cheers, > -Quentin > &...

...classes, because it contains sub-registers of one >>>> of the classes explicitly added to the RegisterBank, for example: >>>> >>>> Added VS_32(explicit (VS_32) VReg_64 class-with-subregs: VReg_64) >>>> >>>> This is a problem, because both RegisterBanks think they cover >>>> VS_32, even though neither of them actually do. >>> >>> I agree this is a bug in the emitter. It should only add the subclasses of VS_32 that projects to V (resp. S) for the given subregs. >>> >>> I let Daniel comment further. &g...

...broad vector support is one on the reason we target O0, i.e., the vectorizer doesn’t run and we are less likely to hit the missing implementation. ** RegBankSelect ** - Core logic is present, no optimizations yet, or more accurately, the greedy mode is still pretty silly. - TableGen support for RegisterBanks description. * What’s Left * - TableGen the instruction mapping from the existing SDISel patterns. - Improve the optimization heuristic. ** InstructionSelect ** - Core logic present. - TableGen support for simple SDISel patterns (i.e., GISel reuses SDISel patterns) * What’s Left * - Teach Ta...

Hi LLVM developers, Don't be quiet :) we need your suggestions for supporting custom CCState, CCAssignFn in D41700. And also RegisterBank in D41653. because it needs to consider about how to support variable-sized register classes concept implemented in D24631. And I think you might have same question when porting to GlobalISel for your Targets, so please give us some directions, thanks

Hi LLVM developers, I am not available from February 11th to February 25th due to Chinese Spring Festival and my sincere thanks goto: Anna Zaks:     She lead me to the LLVM family and reviewed my patch for clang analyzer MallocChecker carefully and patiently. Дуже дякую Artem Dergachev:     He reviewed my patches for clang analyzer some Checkers carefully. Большое спасибо Dylan McKay:

This question came about through reviewing work from Leslie Zhai on GlobalISel support for RISC-V, which also motivated me to revisit code which I've always felt was a bit clunky. Calling convention lowering in LLVM is typically handled by functions conforming to the CCAssignFn typedef: typedef bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT,

Hi Quentin, thank you for the reply! I have a couple more questions that came up when I tried to implement this today. I hope you can help me out with this again! Am 09.03.20 um 23:31 schrieb Quentin Colombet: > I would expect that you could create a register class and register > bank for the special register. That way you have something to map to > when you do register bank select.

Hi all, Over the past few months we’ve been doing work on the foundations for the next stages of GlobalISel development. In terms of changes from this time last year, the IR translator, the legalizer, and instruction selector have seen moderate to major changes. The most significant of these was the change to the legalizer API, allowing targets to use predicates to express legality, which gives