search for: regclassforvt

...e a similar need. -------------- next part -------------- diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index e3e5737..e45b792 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -958,6 +958,14 @@ protected: RegClassForVT[VT.SimpleTy] = RC; } + /// clearRegisterClasses - remove all register classes + void clearRegisterClasses() { + for (unsigned i = 0 ; i<array_lengthof(RegClassForVT); i++) + RegClassForVT[i] = 0; + while (!AvailableRegClasses.empty()) + AvailableRegClasses.pop_back(); + }...

...t;"poi6", 6>; def POI7: X86Reg<"poi7", 7>; def PR128 : RegisterClass<"X86", [i128], 128, (sequence "POI%u", 0, 7)>; However, my debug message in TargetLowering base in its method computeRegisterProperties shows that RegClassForVT[MVT::i128] is still a nullptr. What else should I add for my registers to be a proper destination location of all 128-bit integers? Thanks, Barbora -- ---------------- Barbora Murinová The University of Edinburgh SK: +421905718390 UK: +447477833795 -------------- next part -------------- An HTML...

...o does that mean that LLVM can't lower automatically to 8-bit values? There is no inherent reason. LLVM should be able to lower to 8-bit values. It's probably a bug somewhere. In TargetLowering.h: bool isTypeLegal(MVT::ValueType VT) const { return !MVT::isExtendedVT(VT) && RegClassForVT[VT] != 0; } Is there a 16-bit register class? > I tried defining 8-bit pointers in the subtarget using "p:8:8:8" > but it > asserts at line 566 of TargetData.cpp in the default case of > TargetData::getIntPtrType() Dunno why it's like this. Can you add case 1: retu...

...o does that mean that LLVM can't lower automatically to 8-bit values? There is no inherent reason. LLVM should be able to lower to 8-bit values. It's probably a bug somewhere. In TargetLowering.h: bool isTypeLegal(MVT::ValueType VT) const { return !MVT::isExtendedVT(VT) && RegClassForVT[VT] != 0; } Is there a 16-bit register class? > I tried defining 8-bit pointers in the subtarget using "p:8:8:8" > but it > asserts at line 566 of TargetData.cpp in the default case of > TargetData::getIntPtrType() Dunno why it's like this. Can you add case 1: retu...

So does that mean that LLVM can't lower automatically to 8-bit values? I tried defining 8-bit pointers in the subtarget using "p:8:8:8" but it asserts at line 566 of TargetData.cpp in the default case of TargetData::getIntPtrType() Is it difficult to add 8-bit support? A. -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On

...omatically to 8-bit >> values? > > There is no inherent reason. LLVM should be able to lower to 8-bit > values. It's probably a bug somewhere. > > In TargetLowering.h: > > bool isTypeLegal(MVT::ValueType VT) const { > return !MVT::isExtendedVT(VT) && RegClassForVT[VT] != 0; > } > > Is there a 16-bit register class? > >> I tried defining 8-bit pointers in the subtarget using "p:8:8:8" >> but it >> asserts at line 566 of TargetData.cpp in the default case of >> TargetData::getIntPtrType() > > Dunno why it&...

...omatically to 8-bit >> values? > > There is no inherent reason. LLVM should be able to lower to 8-bit > values. It's probably a bug somewhere. > > In TargetLowering.h: > > bool isTypeLegal(MVT::ValueType VT) const { > return !MVT::isExtendedVT(VT) && RegClassForVT[VT] != 0; > } > > Is there a 16-bit register class? > >> I tried defining 8-bit pointers in the subtarget using "p:8:8:8" >> but it >> asserts at line 566 of TargetData.cpp in the default case of >> TargetData::getIntPtrType() > > Dunno why it&...

...values? >> >> There is no inherent reason. LLVM should be able to lower to 8-bit >> values. It's probably a bug somewhere. >> >> In TargetLowering.h: >> >> bool isTypeLegal(MVT::ValueType VT) const { >> return !MVT::isExtendedVT(VT) && RegClassForVT[VT] != 0; >> } >> >> Is there a 16-bit register class? >> >>> I tried defining 8-bit pointers in the subtarget using "p:8:8:8" >>> but it >>> asserts at line 566 of TargetData.cpp in the default case of >>> TargetData::getIntPt...

On 4/12/2018 8:01 AM, Dominique Torette via llvm-dev wrote: > > But there is one small issue in the inference of RegisterClass of the > implicitly defined register. > > As shown below, the %vreg6<def> is implicitly defined as FPUabRegisterClass. > > This register class accepts the v2f32 type, but for others addressing > mode context this register should be

...values? >> >> There is no inherent reason. LLVM should be able to lower to 8-bit >> values. It's probably a bug somewhere. >> >> In TargetLowering.h: >> >> bool isTypeLegal(MVT::ValueType VT) const { >> return !MVT::isExtendedVT(VT) && RegClassForVT[VT] != 0; >> } >> >> Is there a 16-bit register class? >> >>> I tried defining 8-bit pointers in the subtarget using "p:8:8:8" >>> but it >>> asserts at line 566 of TargetData.cpp in the default case of >>> TargetData::getIntPt...

Hi, I'm implementing the built_vector as an IMPLICIT_DEF followed by INSERT_SUBREGs. This approach is the one of the SPARC architecture. def : Pat<(build_vector (f32 fpimm:$a1), (f32 fpimm:$a2)), (INSERT_SUBREG(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), (i32 (COPY_TO_REGCLASS (MOVSUTO_A_iSLo (bitcast_fpimm_to_i32 f32:$a1)), FPUaOffsetClass)), A_UNIT_PART),