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2018 Apr 10
1
How to finalize instruction lowering after register allocation.
...ers definition point of view, I've first defined the 512 UnitA registers in a RegisterClass RegClassA and the 512 UnitB registers in a RegisterClass RegClassB. In order to defined registers operands for the SIMD version of FPU instructions, I've then defined 512 registers in a RegisterClass RegClassAB. The registers from RegClassAB overlap the one the ones of RegClassA and RegClassB in this way RegClassAB.R1 has two subregisters: RegClassA.R1 and RegClassB.R1. So far, so good. I can generated code for math expression taking advantage of SIMD FPU! My problem is on the implementation of the BUILD...