Displaying 4 results from an estimated 4 matches for "regclassa".
Did you mean:
regclass
2018 Apr 10
1
How to finalize instruction lowering after register allocation.
...R5, R6; // => ACC_B = RegisterB_5 + RegisterB_6
FADD AB R7, R8; // => ACC_A = RegisterA_7 + RegisterA_8 and ACC_B = RegisterB_7 + RegisterB_8
>From a machine registers definition point of view, I've first defined the 512 UnitA registers in a RegisterClass RegClassA and the 512 UnitB registers in a RegisterClass RegClassB.
In order to defined registers operands for the SIMD version of FPU instructions, I've then defined 512 registers in a RegisterClass RegClassAB.
The registers from RegClassAB overlap the one the ones of RegClassA and RegClassB in this way...
2019 Jun 25
2
How to handle ISD::STORE when both operands are FrameIndex?
...e from objects that are still allocated on the stack
> at the time of the SDAG construction. In your case it seems that the
> address and the value to store are both on the stack. You don’t need to do
> anything in particular with it. If you have a selection pattern of form
> “(store RegClassA:$Addr, RegClassB:$Val), (STORE $Addr, $Val)”, then it
> will force loading both, Addr and Val into registers.
>
You mean, LLVM will automagically generate loads? This isn't happening for
me.
And what's "STORE"? Is it somehow different from "store"?
I think someo...
2019 Jun 24
3
How to handle ISD::STORE when both operands are FrameIndex?
Hello.
After "Initial selection DAG" stage I get a DAG with node
t14: ch = store<(store 4 into %ir.p45, align 8, addrspace 1)> t10,
FrameIndex:i32<2>, FrameIndex:i32<3>, undef:i32
1. Where does it come from? Can I do anything to make it not appear?
2. If not, how do I change it so that the operand being stored would be
first loaded into a register, and that register
2019 Jun 26
2
How to handle ISD::STORE when both operands are FrameIndex?
...e from objects that are still allocated on the
> stack at the time of the SDAG construction. In your case it seems that the
> address and the value to store are both on the stack. You don’t need to do
> anything in particular with it. If you have a selection pattern of form
> “(store RegClassA:$Addr, RegClassB:$Val), (STORE $Addr, $Val)”, then it
> will force loading both, Addr and Val into registers.
> >
> > You mean, LLVM will automagically generate loads? This isn't happening
> for me.
>
> "Materializing" would probably have been a less ambiguous...