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Hi, Assume I define registers R0...R15 and two register classes RegA and RegB. RegA contains R0 to R7 while RegB contains R0 to R15. Then I check the machine instruction, it seems that in some cases, the %vreg0 belongs to RegB; in other cases %vreg1 belongs to RegA_RegB. Can you tell me how TableGen decides which is which? At first, I guess &verg0 will be assigned by R8...

.... I've define the following semantic to my architecture specific instructions: def MOVSUTO_SU_rr : CLPSUInst_rr<0b1000001100, (ins SURegisterOperand:$RegA), (outs SURegisterOperand:$RegB), [], "movsuto_su\t$RegA,$RegB","RR", [(store (i16 SURegisterOperand:$RegA), i16:$RegB)], NoItinerary> {...

...MBB_erase->addSuccessor(MBB_cond); MBB_erase->addSuccessor(MBB_end); MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); unsigned regA = MRI.createVirtualRegister(AddrRegClass); unsigned regB = MRI.createVirtualRegister(AddrRegClass); unsigned regC = MRI.createVirtualRegister(AddrRegClass); // Set the indice BuildMI(*MBB, MI, db, TII->get(X86::MOV64rr)).addReg(regA).addReg(X86::RSP); // Check condition BuildMI(*MBB_cond, MBB_cond->end(), db, TII->get(X86::...

...there is a pass in code gen that replaces index increment with lea. Here is the snippet from llvm/lib/CodeGen/TwoAddressInstructionPass.cpp if (MI.isConvertibleTo3Addr()) { // This instruction is potentially convertible to a true // three-address instruction. Check if it is profitable. if (!regBKilled || isProfitableToConv3Addr(regA, regB)) { // Try to convert it. if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) { ++NumConvertedTo3Addr; return true; // Done with this instruction. } } } regBKilled is false for my test case and isProfitableToConv3Addr is not even...

...() { %ptr = alloca i32 store volatile i32 12, i32* %ptr ret void } The target instruction is associated to the store like this: def MOVSUTO_A_iSLr : CLPFPU_A_iSLr<0b1000001101, (ins IMM32Operand:$ImmA, FPUaRegisterOperand:$RegB), (outs ), [], "movsuto_a\t$ImmA,$RegB", [(store i32:$ImmA, i16:$RegB)],NoItinerary> { The s...

...@@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg(); TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI, *TRI); ReMatRegs.set(TargetRegisterInfo::virtReg2Index(regB)); ++NumReMats; } else { - BuildMI(*mbbi, mi, mi->getDebugLoc(), TII->get(TargetOpcode::COPY), - regA).addReg(regB); + unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg(); + if (regASubIdx) { +...

...e code? > > I'm not sure what you mean. It definitely does run on machine code. I was thinking that it only transformed instructions with virtual registers because of this code in the TwoAddressInstructionPass.cpp: unsigned regA = mi->getOperand(0).getReg(); unsigned regB = mi->getOperand(1).getReg(); assert(MRegisterInfo::isVirtualRegister(regA) && MRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"); By machine code I meant code with virtual registers, ins...

...ith lea. > > Here is the snippet from llvm/lib/CodeGen/TwoAddressInstructionPass.cpp > > > > if (MI.isConvertibleTo3Addr()) { > > // This instruction is potentially convertible to a true > > // three-address instruction. Check if it is profitable. > > if (!regBKilled || isProfitableToConv3Addr(regA, regB)) { > > // Try to convert it. > > if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) { > > ++NumConvertedTo3Addr; > > return true; // Done with this instruction. > > } > > } > > } > &g...

...MBB_erase->addSuccessor(MBB_end); >> >> MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); >> const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); >> unsigned regA = MRI.createVirtualRegister(AddrRegClass); >> unsigned regB = MRI.createVirtualRegister(AddrRegClass); >> unsigned regC = MRI.createVirtualRegister(AddrRegClass); >> >> // Set the indice >> BuildMI(*MBB, MI, db, >> TII->get(X86::MOV64rr)).addReg(regA).addReg(X86::RSP); >> >> // Check condition >&gt...

...llvm/lib/CodeGen/TwoAddressInstructionPass.cpp >> >> >> >> if (MI.isConvertibleTo3Addr()) { >> >> // This instruction is potentially convertible to a true >> >> // three-address instruction. Check if it is profitable. >> >> if (!regBKilled || isProfitableToConv3Addr(regA, regB)) { >> >> // Try to convert it. >> >> if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) { >> >> ++NumConvertedTo3Addr; >> >> return true; // Done with this instruction. >> >&gt...

...(IsRegOrSuperReg) { PRI.Defines = true; // Reg or a super-register is defined. if (!MO.isDead()) AllDefsDead = false; } I think the fundamental bug here is that the operands are swapped when passed into isSuperRegister. The definition of isSuperRegister is /// \brief Returns true if RegB is a super-register of RegA. bool isSuperRegister(unsigned RegA, unsigned RegB) const; so, it looks to me as if in the call to isSuperRegister, the parameters are swapped, and analyzePhysReg should really be asking whether the operand Reg (MOReg) is a super register of Reg, and the code should be:...

...onPass.cpp >>> >>> >>> >>> if (MI.isConvertibleTo3Addr()) { >>> >>> // This instruction is potentially convertible to a true >>> >>> // three-address instruction. Check if it is profitable. >>> >>> if (!regBKilled || isProfitableToConv3Addr(regA, regB)) { >>> >>> // Try to convert it. >>> >>> if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) { >>> >>> ++NumConvertedTo3Addr; >>> >>> return true; // Done with this in...

...not sure what you mean. It definitely does run on machine code. > > I was thinking that it only transformed instructions with virtual > registers because of this code in the TwoAddressInstructionPass.cpp: > > unsigned regA = mi->getOperand(0).getReg(); > unsigned regB = mi->getOperand(1).getReg(); > > assert(MRegisterInfo::isVirtualRegister(regA) && > MRegisterInfo::isVirtualRegister(regB) && > "cannot update physical register live information"); > > By machine code I meant code wi...

...y corresponding to the leaf registers. (Those without any sub-registers). A target has fewer register units than registers, and forming pseudo-super-registers to model constraints doesn't create more register units. Each register is assigned a list of register units such that: RegA overlaps RegB if and only if Units(RegA) intersects Units(RegB). On X86, for example, the register units are the 8-bit registers: AH, AL, BH, BL, … The 64-bit register %rax is assigned units (AH, AL), and so is %eax. It is easy to check that %rax and %eax overlaps because they have the same register units. In g...

On Mon, 26 Jun 2006, Fernando Magno Quintao Pereira wrote: > Thank you Chris. I will try to implement the TwoAddress pass to run on > machine code. Why it has not been originally implemented to run on > machine code? I'm not sure what you mean. It definitely does run on machine code. > Is there anything that makes it troublesome after RA > has been performed? Do you

Thank you Chris. I will try to implement the TwoAddress pass to run on machine code. Why it has not been originally implemented to run on machine code? Is there anything that makes it troublesome after RA has been performed? Could you tell me if the transformations below are correct? 1) a := b op c --> a := b --> a := b a := a op c a

...ists.cs.uiuc.edu/pipermail/llvmdev/2006-October/006892.html but was wondering if anyone could comment on this process in a little more detail. I presume I need to define various target independent nodes, like below ... def SDT_SABREcondbr : SDTypeProfile<0,3, // no result, 3 operands, rega, regb, immediate [ SDTCisVT<1,i32>, SDTCisVT<2,OtherVT> ]>; def SABREcondbranch: SDNode <"SABREISD::COND_BRANCH" , SDT_SABREcondbr, [SDNPHasChain]>; def COND_BRANCH: Pseudo<(ops IntRegs:$a, IntRegs:$b, target:$dst), "${:comment}CO...

...(IsRegOrSuperReg) { PRI.Defines = true; // Reg or a super-register is defined. if (!MO.isDead()) AllDefsDead = false; } I think the fundamental bug here is that the operands are swapped when passed into isSuperRegister. The definition of isSuperRegister is /// \brief Returns true if RegB is a super-register of RegA. bool isSuperRegister(unsigned RegA, unsigned RegB) const; so, it looks to me as if in the call to isSuperRegister, the parameters are swapped, and analyzePhysReg should really be asking whether the operand Reg (MOReg) is a super register of Reg, and the code should be:...

...======================================== --- lib/CodeGen/TwoAddressInstructionPass.cpp (revision 71041) +++ lib/CodeGen/TwoAddressInstructionPass.cpp (working copy) @@ -935,6 +935,7 @@ ++NumReMats; } else { bool Emitted = TII->copyRegToReg(*mbbi, mi, regA, regB, rc, rc); + (void)Emitted; assert(Emitted && "Unable to issue a copy instruction! \n"); } in a release-asserts build to get around a warning: /Volumes/mrs5/net/clang/clang/clang/lib/CodeGen/ TwoAddressInstructionPass.cpp: In member functi...

> On Dec 3, 2015, at 5:36 PM, Quentin Colombet via llvm-dev <llvm-dev at lists.llvm.org> wrote: > >> >> On Dec 3, 2015, at 5:11 PM, Smith, Kevin B <kevin.b.smith at intel.com <mailto:kevin.b.smith at intel.com>> wrote: >> >> >> >>> -----Original Message----- >>> From: Quentin Colombet [mailto:qcolombet at apple.com