search for: regalloc

...viously much more work needs to be done before a patch based on these experimental results can be submitted. For example, I have done no testing on non-X86 targets. However, at this point I would welcome opinions and suggestions! Thanks, Rob. *** Register Allocator Statistics Unmodified: 32 regalloc - Number of copies inserted for splitting 2 regalloc - Number of folded loads 3 regalloc - Number of folded stack accesses 19 regalloc - Number of identity moves eliminated after rewriting 18 regalloc - Number of instructions deleted by DCE 158 regalloc - Nu...

Hi LLVM, I ran into a case where RegAlloc would insert a spill across instruction that had same register for output operand and implicit-def. The effect this had was that spill code would immediately overwrite the output result. Is this the expected result of setting up MyInst this way? In other words, does RegAlloc know to not insert...

...; > Could you file a public report? > > Thanks, > -Quentin > >> On May 6, 2019, at 3:13 PM, Kevin Choi via llvm-dev >> <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >> >> Hi LLVM, >> >> I ran into a case where RegAlloc would insert a spill across >> instruction that had same register for output operand and >> implicit-def. The effect this had was that spill code would >> immediately overwrite the output result. Is this the expected result >> of setting up MyInst this way? In other word...

...hine function. Each machine > function contains many basic blocks. If a program has many functions, the > register allocator will be called as many times, i.e it does not do > interprocedural allocation. > > best, > > Fernando Thanks for replying back. I am looking to write a regalloc pass that does interprocedural regalloc. By constructing a Call Graph and keeping the registers in a single call chain different so that i can avoid spilling (saving) across function calls. What will be the right place to do so? Sanjiv > As far as I understand , the regalloc passes provided op...

Thanks again. One more question here: Since the regalloc works once per function, do I stil have access to the Call graph? Just saving information between regalloc passes for different functions may not be enough for my case. I will need to maintain the regalloc info of various passes in the call graph order. Anyways thanks for your inputs. I will get ba...

Great! I thought I had to look at our pipeline at O0 to make sure optimized regalloc was supported (https://bugs.llvm.org/show_bug.cgi?id=33022 <https://bugs.llvm.org/show_bug.cgi?id=33022> in mind). Glad I was wrong, it saves me some time. > On May 22, 2017, at 12:51 AM, Kristof Beyls <kristof.beyls at arm.com> wrote: > > >> On 22 May 2017, at 09:09,...

...BJDIR. The problem is that it only add to llc the changes on the lib/CodeGen directory. If you change other parts, a make from LLVMOBJDIR will synchronize it. Try adding code like this to your Passes.cpp file: //===---------------------------------------------------------------------===// /// /// RegAlloc command line options. /// //===---------------------------------------------------------------------===// namespace { cl::opt<RegisterRegAlloc::FunctionPassCtor, false, RegisterPassParser<RegisterRegAlloc> > RegAlloc("regalloc", cl::init(&createCho...

...ions. Using version 3.3 the current register allocators available to use are "basic, fast, greedy and pbqp". However, I'm facing the following issues: 1) I can't run basic and PBQP allocators using the command line flags of the dragonegg (-fplugin-arg-dragonegg-llvm-option="-regalloc:basic"). I get this error message "for the -regalloc option: Cannot find option named 'pbqp'!" or basic. Note that I didn't get this error when I used the LLC tool. 2) I can't run the fast register allocator while using the "O1/O2/O3" optimizations flags. I...

...istof Beyls <kristof.beyls at arm.com> wrote: > >> >> On 23 May 2017, at 21:48, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote: >> >> Great! >> I thought I had to look at our pipeline at O0 to make sure optimized regalloc was supported (https://bugs.llvm.org/show_bug.cgi?id=33022 <https://bugs.llvm.org/show_bug.cgi?id=33022> in mind). Glad I was wrong, it saves me some time. >> >>> On May 22, 2017, at 12:51 AM, Kristof Beyls <kristof.beyls at arm.com <mailto:kristof.beyls at arm.com>&g...

Hi, again, I think you can do it in the same way that the other allocators have been coded, i.e extend RA, register the pass and so forth. I am not sure about the best way to pass information among a run of RegAlloc to the other, maybe the other guys in the list could suggest something. Yet, you can always dump it into a file, and read it again, everytime it is necessary. Remember that RegAlloc will be called once per function. Also, LLVM does very aggressive inlining of method calls, and this may cause th...

...odegenComponents.h" . Another note: with this new functionality you should be able to dynamically load register allocators. Build your register allocator into a dynamic library, like this: http://llvm.org/docs/WritingAnLLVMPass.html#makefile They you should be able to use: llc -load yourregalloc.so -regalloc=yours ... -Chris -- http://nondot.org/sabre/ http://llvm.org/

Hi! I've did what Jim Laskey wrote but llc didn't reckognize my regalloc option. So I moved my allocator implementation into seperate folder within CodeGen and wrote separate makefile for it (like in "Writing an LLVM pass" tutorial). But when I run "make" from LLVMOBJDIR it doesn't enter the RegAlloc directory and when linking llc an error like...

Hi! I developed a register allocator within LLVM and now I need to test its efficiency. Can I do this using llvm-test package? Do llvm tests check all available regalloc options automatically? If not, then what modifications should I do to the test files? It would be great if I could test my algo along with linearscan and compare the results. Thanks. Tony. -- "Nae king! Nae quin! Nae laird! Nae master! We willnae be fooled again!", Nac Mac Feegles (Te...

...STDWPtrQRr <fi#15>, 0, %R19R18; mem:ST2[FixedStack15](align=1) STDWPtrQRr <fi#15>, 0, %R19R18; mem:ST2[FixedStack15](align=1) Each STDWPtrQRr is a spill instruction, but notice that it's spilling everything twice to each frame index. I'm only getting this with the Greedy regalloc, PBQP will not duplicate the spills. Is there something here that I'm missing or could it be a bug? I haven't attached the C code now to not spam the message or the huge debug output of the regalloc, but I will supply any information as requested. Thanks -------------- next part ----------...

On May 24, 2011, at 8:22 AM, Jonas Paulsson wrote: > Hi (Jakob), > > in reference to the prior message below, I have the following follow-up questions, as I also need a scheduling pass > prior to regalloc. I need to do this in order to set VLIW-flags, so that the RA is aware of several MI's > per cycle with a redefined LiveRange::overlap-function. On a multiple-issue cycle, a register that gets killed > can be reused by another MI - these live ranges do not then overlap. Redefining overla...

...lt;fi#15>, 0, %R19R18; mem:ST2[FixedStack15](align=1) > STDWPtrQRr <fi#15>, 0, %R19R18; mem:ST2[FixedStack15](align=1) > > Each STDWPtrQRr is a spill instruction, but notice that it's spilling everything twice to each frame index. I'm only getting this with the Greedy regalloc, PBQP will not duplicate the spills. > Is there something here that I'm missing or could it be a bug? I haven't attached the C code now to not spam the message or the huge debug output of the regalloc, but I will supply any information as requested. Did you implement isStoreToStackSlot(...

...>> Thanks for the measurements. >> >>> On May 24, 2017, at 6:00 AM, Kristof Beyls <kristof.beyls at arm.com <mailto:kristof.beyls at arm.com>> wrote: >>> >>>> >>>>> - Comparing against -O0 without globalisel but with the above regalloc options: 5.6% performance drop, 1% code size drop. >>>>> >>>>> In summary, the measurements indicate some good improvements. >>>>> I also haven't measure the impact on compile time. >>>> >>>> Do you have a mean to make this...

> Hi! > > I developed a register allocator within LLVM and now I need to test its > efficiency. Can I do this using llvm-test package? > Do llvm tests check all available regalloc options automatically? If not, > then what modifications should I do to the test files? > It would be great if I could test my algo along with linearscan and compare > the results. > > Thanks. > > Tony. Hey, Anton. In TEST.llc.Makefile, you can set the type of register al...

...ords, as long as you use different opcodes for widen-op NN and > widen-op WN, you model exactly what you want. > > What am I missing? > we are using different opcodes for widen-op NN and widen-op WN. My understanding is that not setting earlyclobber to the W, N variant would allow the RegAlloc to do an allocation like this W1 = widen-op W2, N3 but this is not correct in that target because W1 and N3 are of different kind and W1 (being the group of registers N2, N3) overlaps N3. If I understand earlyclobber semantics correctly, earlyclobber would allocate the destination to something t...

Hi (Jakob), in reference to the prior message below, I have the following follow-up questions, as I also need a scheduling pass prior to regalloc. I need to do this in order to set VLIW-flags, so that the RA is aware of several MI's per cycle with a redefined LiveRange::overlap-function. On a multiple-issue cycle, a register that gets killed can be reused by another MI - these live ranges do not then overlap. Well, I would like to sched...