search for: rega

Hi, Assume I define registers R0...R15 and two register classes RegA and RegB. RegA contains R0 to R7 while RegB contains R0 to R15. Then I check the machine instruction, it seems that in some cases, the %vreg0 belongs to RegB; in other cases %vreg1 belongs to RegA_RegB. Can you tell me how TableGen decides which is which? At first, I guess &verg0 will be assig...

...tried to map the ISel 'Store' node to architecture specific instructions. I've define the following semantic to my architecture specific instructions: def MOVSUTO_SU_rr : CLPSUInst_rr<0b1000001100, (ins SURegisterOperand:$RegA), (outs SURegisterOperand:$RegB), [], "movsuto_su\t$RegA,$RegB","RR", [(store (i16 SURe...

...gt; > Lease=read.csv("lease.csv", header=TRUE) > Lease$ET <- factor(Lease$EarlyTermination) > SICCode=factor(Lease$SIC.Code) > Lease$TO=factor(Lease$TenantHasOption) > Lease$LO=factor(Lease$LandlordHasOption) > Lease$TEO=factor(Lease$TenantExercisedOption) > > RegA=glm(ET~1+TO, + family=binomial(link=logit), data=Lease) > summary(RegA) Call: glm(formula = ET ~ 1 + TO, family = binomial(link = logit), data = Lease) Deviance Residuals: Min 1Q Median 3Q Max -0.5839 -0.5839 -0.5839 -0.3585 2.3565 Coefficients: E...

...The two changes below improves the situation for me but I'm all new to this so I'm not sure how it's supposed to work. I'm running on 2.9. Any comments? @@ -1172,12 +1172,20 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg(); TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI, *TRI); ReMatRegs.set(TargetRegisterInfo::virtReg2Index(regB)); ++NumReMats; } else { - BuildMI(*mbbi, mi, mi->getDebugLoc(),...

...ces index increment with lea. Here is the snippet from llvm/lib/CodeGen/TwoAddressInstructionPass.cpp if (MI.isConvertibleTo3Addr()) { // This instruction is potentially convertible to a true // three-address instruction. Check if it is profitable. if (!regBKilled || isProfitableToConv3Addr(regA, regB)) { // Try to convert it. if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) { ++NumConvertedTo3Addr; return true; // Done with this instruction. } } } regBKilled is false for my test case and isProfitableToConv3Addr is not even called. I've made an experiment a...

...been originally implemented to run on > > machine code? > > I'm not sure what you mean. It definitely does run on machine code. I was thinking that it only transformed instructions with virtual registers because of this code in the TwoAddressInstructionPass.cpp: unsigned regA = mi->getOperand(0).getReg(); unsigned regB = mi->getOperand(1).getReg(); assert(MRegisterInfo::isVirtualRegister(regA) && MRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"); B...

...from llvm/lib/CodeGen/TwoAddressInstructionPass.cpp > > > > if (MI.isConvertibleTo3Addr()) { > > // This instruction is potentially convertible to a true > > // three-address instruction. Check if it is profitable. > > if (!regBKilled || isProfitableToConv3Addr(regA, regB)) { > > // Try to convert it. > > if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) { > > ++NumConvertedTo3Addr; > > return true; // Done with this instruction. > > } > > } > > } > > > > regBKilled is false for m...

...-censored (i.e. has values below the detection limit). I have been using the NADA package of R to derive summary statistics and do some regression. I am now trying to carry out regression on paired data where both my X and Y have left-censored data within them. I have tried various commands in R: rega = cenreg(Cen(conc, cens_ind) ~ Gp_ident))? with all X and Y data stacked and using a group identifier to look at the differences this doesn't take account of the paired data though. I have also tried splitting the data and regessing one on the other rega = cenreg(Cen(conc1, censind1) ~ Cen(c...

...you very much! Best, Ed > Lease=read.csv("lease.csv", header=TRUE) > Lease$ET = factor(Lease$EarlyTermination) > SICCode=factor(Lease$SIC.Code) > TO=factor(Lease$TenantHasOption) > LO=factor(Lease$LandlordHasOption) > TEO=factor(Lease$TenantExercisedOption) > > RegA=glm(ET~1+MSA, + family=binomial(link=logit), data=Lease, weights=Origil.SQFT) Warning messages: 1: Algorithm did not converge in: glm.fit(x = X, y = Y, weights = weights, start = start, etastart = etastart, 2: fitted probabilities numerically 0 or 1 occurred in: glm.fit(x = X, y = Y, weights =...

...MBB_end); >> MBB_erase->addSuccessor(MBB_cond); >> MBB_erase->addSuccessor(MBB_end); >> >> MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); >> const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); >> unsigned regA = MRI.createVirtualRegister(AddrRegClass); >> unsigned regB = MRI.createVirtualRegister(AddrRegClass); >> unsigned regC = MRI.createVirtualRegister(AddrRegClass); >> >> // Set the indice >> BuildMI(*MBB, MI, db, >> TII->get(X86::MOV64rr)).addReg(re...

The two address pass is only concerned about register pressure. It sounds like it should be taught about profitability. In cases where profitability can only be determined with something machinetracemetric then it probably should live it to more sophisticated pass like regalloc. In this case, we probably need a profitability target hook which knows about lea. We should also consider disabling it's dumb pseudo scheduling code when we enable MI scheduler. Evan Sent from my iPad > On Oct 2, 2013, at 8:38 AM, Rafael Espíndola <rafael.espindola at gmail.com...

...essor(MBB_erase); MBB_cond->addSuccessor(MBB_end); MBB_erase->addSuccessor(MBB_cond); MBB_erase->addSuccessor(MBB_end); MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); unsigned regA = MRI.createVirtualRegister(AddrRegClass); unsigned regB = MRI.createVirtualRegister(AddrRegClass); unsigned regC = MRI.createVirtualRegister(AddrRegClass); // Set the indice BuildMI(*MBB, MI, db, TII->get(X86::MOV64rr)).addReg(regA).addReg(X86::RSP); // Check condition...

...efines = true; // Reg or a super-register is defined. if (!MO.isDead()) AllDefsDead = false; } I think the fundamental bug here is that the operands are swapped when passed into isSuperRegister. The definition of isSuperRegister is /// \brief Returns true if RegB is a super-register of RegA. bool isSuperRegister(unsigned RegA, unsigned RegB) const; so, it looks to me as if in the call to isSuperRegister, the parameters are swapped, and analyzePhysReg should really be asking whether the operand Reg (MOReg) is a super register of Reg, and the code should be: bool IsRegOrSuperReg = MOR...

Dear list, I try to update the prabclus package. R CMD check works nicely, no warnings, good results in all tests. However, building the package fails: ginkgo:/disk5/home/chrish/RAusw/libsrc R CMD build prabclus * checking for file 'prabclus/DESCRIPTION' ... OK * preparing 'prabclus': * checking whether 'INDEX' is up-to-date ... OK * removing junk files * building

...one) Win7 is installed in the vm. This calling path is executed so frequent that may come down to set the RTC's REG_A hundreds of times every second but with the same rate(976.562us(1024HZ)), it is so abnormal to me to see such behavior. 3 OS I have tried to find why the win7 setted RTC's regA so frequently. finally got the result, all that comes from a function: NtSetTimerResolution --> 0x70,0x71 when I attached windbg into the guest OS, I also found the source, they are all called from a upper system call that comes from JVM(Java Virtual Machine). 4 JVM I don't know why JVM cal...

...t apple.com> wrote: > The two address pass is only concerned about register pressure. It sounds like it should be taught about profitability. In cases where profitability can only be determined with something machinetracemetric then it probably should live it to more sophisticated pass like regalloc. > > In this case, we probably need a profitability target hook which knows about lea. We should also consider disabling it's dumb pseudo scheduling code when we enable MI scheduler. Sorry, I set this aside to look at closely and never got back to it. The lea->cmp problem is f...

...un on >>> machine code? >> >> I'm not sure what you mean. It definitely does run on machine code. > > I was thinking that it only transformed instructions with virtual > registers because of this code in the TwoAddressInstructionPass.cpp: > > unsigned regA = mi->getOperand(0).getReg(); > unsigned regB = mi->getOperand(1).getReg(); > > assert(MRegisterInfo::isVirtualRegister(regA) && > MRegisterInfo::isVirtualRegister(regB) && > "cannot update physical register live in...

...#39;, typically corresponding to the leaf registers. (Those without any sub-registers). A target has fewer register units than registers, and forming pseudo-super-registers to model constraints doesn't create more register units. Each register is assigned a list of register units such that: RegA overlaps RegB if and only if Units(RegA) intersects Units(RegB). On X86, for example, the register units are the 8-bit registers: AH, AL, BH, BL, … The 64-bit register %rax is assigned units (AH, AL), and so is %eax. It is easy to check that %rax and %eax overlaps because they have the same regist...

...ls (this=0x80630b0) at ../lib/CodeGen/LiveIntervals.cpp:493 493 assert(r2iA != r2iMap_.end()); The instruction it crashes is: (gdb) p $4.dump() %reg1056 = move %gr7 And gr7 is exactly the register which is looked up with Reg2IntervalMap::iterator r2iA = r2iMap_.find(regA) on line 492. I'm not sure the about the logic, but seems the code tries to map register into live interval, and since the above gr7 is inserted by code selector (it's return value from a function), it's not wonder no interval is found. I've worked this around by making isMoveI...

On Mon, 26 Jun 2006, Fernando Magno Quintao Pereira wrote: > Thank you Chris. I will try to implement the TwoAddress pass to run on > machine code. Why it has not been originally implemented to run on > machine code? I'm not sure what you mean. It definitely does run on machine code. > Is there anything that makes it troublesome after RA > has been performed? Do you