Displaying 2 results from an estimated 2 matches for "reg_imm".
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reg_i
2015 Sep 18
5
multiply-accumulate instruction
...arly but performs signed multiply and accumulate. The MAC instructions execute in one clock but have two clocks latency, meaning that one pipeline stall cycle will be inserted if the following instruction uses the destination register of the MAC as a source operand.
Assembler syntax:
smac rs1, reg_imm, rd
Operation:
prod[31:0] = rs1[15:0] * reg_imm[15:0]
result[39:0] = (Y[7:0] & %asr18[31:0]) + prod[31:0]
(Y[7:0] & %asr18[31:0]) = result[39:0]
rd = result[31:0]
%asr18 can be read and written using the rdasr and wrasr instructions.
===
I have the following in SparcInstr...
2015 Sep 21
2
multiply-accumulate instruction
...arly but performs signed multiply and accumulate. The MAC instructions execute in one clock but have two clocks latency, meaning that one pipeline stall cycle will be inserted if the following instruction uses the destination register of the MAC as a source operand.
Assembler syntax:
smac rs1, reg_imm, rd
Operation:
prod[31:0] = rs1[15:0] * reg_imm[15:0]
result[39:0] = (Y[7:0] & %asr18[31:0]) + prod[31:0]
(Y[7:0] & %asr18[31:0]) = result[39:0]
rd = result[31:0]
%asr18 can be read and written using the rdasr and wrasr instructions.
===
I have the following in SparcInstr...