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Here basically my problem is vector width since i have used v64i32 in my backend. now if vector width=64. i want the Reg_B class registers to be assigned and if vector width=2048 i want Reg_A registers to be assigned to instruction. Should i incorporate the solution in lowering stage? some thing like; addRegisterClass(MVT::v2048i32, &X86::Reg_B); setOperationAction(ISD::MNLOAD, MVT::v...

...o something as follows: 1st load to take place in R_0_V_0 2nd load to take place in R_1_V_0 3rd load to take place in R_2_V_0 Now, how to achieve this? Can i mention some condition in instructioninfo.td file? and in registerinfo.td file instead of 1 object Reg_A, there will be 2 objects Reg_A and Reg_B where Reg_B defines same registers but in different order. Reg_B; R_0_V_0, R_1_V_0, R_2_V_0, //here R changes R_0_V_1, R_1_V_1, R_2_V_1, R_0_V_2, R_1_V_2, R_2_V_2, R_0_V_3, R_1_V_3, R_2_V_3. So that in instructioninfo.td file it will be something like; if (no of iterations>=4) load ..........

...e; I now have support for v2048i32 but my backend supports v64i32 so ultimately v2048i32 needs to be split into 32 v64i32 instructions. the only difference between 2 is if its orginally v2048i32 i want my registers assignment from REG_A set. if its v64i32 originally, then i want registers from set REG_B. How to accomplish this??? I am really stuck at this point. Please guide me. Thank You On Tue, Jul 11, 2017 at 6:20 PM, Hal Finkel <hfinkel at anl.gov> wrote: > > On 07/11/2017 03:22 AM, hameeza ahmed wrote: > >> Hello, >> >> i want to work with these types...

...but my backend supports v64i32 >> so ultimately v2048i32 needs to be split into 32 v64i32 instructions. the >> only difference between 2 is if its orginally v2048i32 i want my registers >> assignment from REG_A set. if its v64i32 originally, then i want registers >> from set REG_B. >> >> >> How to accomplish this??? >> >> I am really stuck at this point. >> >> Please guide me. >> >> Thank You >> >> >> On Tue, Jul 11, 2017 at 6:20 PM, Hal Finkel <hfinkel at anl.gov> wrote: >> >>> >...

Hello, i want to work with these types v32f32, v32f64.... in llvm which are undefined in the backend? But v32i32, v32i64 are already defined so i am able to use these. but for other types such as v32f32, v32f64 although i have defined them appropriately in all the files like machinevaluetype.h, valuetypes.cpp etc. i have checked it many times but still getting the following error when build in

Dear all: I have found a big bug on xen concerning time virtualization. Please let me show you the whole process: 1 Phenomenon when I run a JVM based program in IE browser in my Virtual Machine, I have found clearly that time at the right bottom corner in my VM gets more slower and slower. I studied the bug deeply, and found something below. 2 Xen vmx_vmexit_handler --> ......... -->

...testing - don''t expose the reported lockup; the 7th will need debugging to understand what''s wrong there. 1: use RTC_* names instead of literal numbers 2: consolidate toggling of RTC IRQ 3: adjust rtc_timer_update() 4: fix RTC hour conversions 5: used cached original value in RTC_REG_B writing code 6: generalize IRQ raising on RTC_REG_B writes Signed-off-by: Jan Beulich <jbeulich@suse.com>