search for: reg_a

Here basically my problem is vector width since i have used v64i32 in my backend. now if vector width=64. i want the Reg_B class registers to be assigned and if vector width=2048 i want Reg_A registers to be assigned to instruction. Should i incorporate the solution in lowering stage? some thing like; addRegisterClass(MVT::v2048i32, &X86::Reg_B); setOperationAction(ISD::MNLOAD, MVT::v2048i32, custom); then in function LowerOperation(SDValue Op, Select...

hello, i have a situation where i have to assign the registers to instructions based on the loop iterations. for eg.. the registers are: R_0_V_0, R_0_V_1, R_0_V_2, R_0_V_3, R_1_V_0, R_1_V_1, R_1_V_2, R_1_V_3, R_2_V_0, R_2_V_1, R_2_V_2, R_2_V_3. These registers defined in object Reg_A These are total 12 registers. will use them contiguously, here i define it in above mentioned order i.e changing V first then R. for eg; if no of iterations>=4. 1st load will take place in R_0_V_0 2nd load will take place in R_0_V_1 3rd load will take place in R_0_V_2 4th load will take plac...

...rtual Machine, I have found clearly that time at the right bottom corner in my VM gets more slower and slower. I studied the bug deeply, and found something below. 2 Xen vmx_vmexit_handler --> ......... --> handle_rtc_io --> rtc_ioport_write --> rtc_timer_update --> set RTC's REG_A to a high rate--> create_periodic_time(disable the former timer, and init a new one) Win7 is installed in the vm. This calling path is executed so frequent that may come down to set the RTC's REG_A hundreds of times every second but with the same rate(976.562us(1024HZ)), it is so abnormal to...

...ank you so much. it run fine. Can you please resolve following issue; I now have support for v2048i32 but my backend supports v64i32 so ultimately v2048i32 needs to be split into 32 v64i32 instructions. the only difference between 2 is if its orginally v2048i32 i want my registers assignment from REG_A set. if its v64i32 originally, then i want registers from set REG_B. How to accomplish this??? I am really stuck at this point. Please guide me. Thank You On Tue, Jul 11, 2017 at 6:20 PM, Hal Finkel <hfinkel at anl.gov> wrote: > > On 07/11/2017 03:22 AM, hameeza ahmed wrote: &gt...

...following issue; >> >> I now have support for v2048i32 >> but my backend supports v64i32 >> so ultimately v2048i32 needs to be split into 32 v64i32 instructions. the >> only difference between 2 is if its orginally v2048i32 i want my registers >> assignment from REG_A set. if its v64i32 originally, then i want registers >> from set REG_B. >> >> >> How to accomplish this??? >> >> I am really stuck at this point. >> >> Please guide me. >> >> Thank You >> >> >> On Tue, Jul 11, 2017 at 6:2...

Hello, i want to work with these types v32f32, v32f64.... in llvm which are undefined in the backend? But v32i32, v32i64 are already defined so i am able to use these. but for other types such as v32f32, v32f64 although i have defined them appropriately in all the files like machinevaluetype.h, valuetypes.cpp etc. i have checked it many times but still getting the following error when build in