Displaying 16 results from an estimated 16 matches for "regf64".
2011 Aug 24
1
[LLVMdev] proposal: add macro expansion of for-loop to TableGen
...!strconcat(opcstr, ".f32\t$d, $a, $b, $c"),
[(set RegF32:$d, (opnode2 (opnode1 RegF32:$a,
RegF32:$b),
fpimm:$c))]>;
def rrr64 : InstPTX<(outs RegF64:$d),
(ins RegF64:$a, RegF64:$b, RegF64:$c),
!strconcat(opcstr, ".f64\t$d, $a, $b, $c"),
[(set RegF64:$d, (opnode2 (opnode1 RegF64:$a,
RegF64:$b),...
2011 Oct 07
6
[LLVMdev] Enhancing TableGen
...!strconcat(opcstr, "$r.f32\t$d, $a, $b"), []>;
> def ri32 : InstPTX<(outs RegF32:$d),
> (ins RndMode:$r, RegF32:$a, f32imm:$b),
> !strconcat(opcstr, "$r.f32\t$d, $a, $b"), []>;
> def rr64 : InstPTX<(outs RegF64:$d),
> (ins RndMode:$r, RegF64:$a, RegF64:$b),
> !strconcat(opcstr, "$r.f64\t$d, $a, $b"), []>;
> def ri64 : InstPTX<(outs RegF64:$d),
> (ins RndMode:$r, RegF64:$a, f64imm:$b),
> !st...
2011 Oct 07
0
[LLVMdev] Enhancing TableGen
...$b),
!strconcat(opcstr, "$r.f32\t$d, $a, $b"), []>;
def ri32 : InstPTX<(outs RegF32:$d),
(ins RndMode:$r, RegF32:$a, f32imm:$b),
!strconcat(opcstr, "$r.f32\t$d, $a, $b"), []>;
def rr64 : InstPTX<(outs RegF64:$d),
(ins RndMode:$r, RegF64:$a, RegF64:$b),
!strconcat(opcstr, "$r.f64\t$d, $a, $b"), []>;
def ri64 : InstPTX<(outs RegF64:$d),
(ins RndMode:$r, RegF64:$a, f64imm:$b),
!strconcat(opcstr, "$r....
2011 Oct 07
0
[LLVMdev] Enhancing TableGen
...binary_pattern<opcstrm "f32">.pattern, []>;
> def ri32 : InstPTX<(outs RegF32:$d),
> (ins RndMode:$r, RegF32:$a, f32imm:$b),
> binary_pattern<opcstrm "f32">.pattern, []>;
> def rr64 : InstPTX<(outs RegF64:$d),
> (ins RndMode:$r, RegF64:$a, RegF64:$b),
> binary_pattern<opcstrm "f64">.pattern, []>;
> def ri64 : InstPTX<(outs RegF64:$d),
> (ins RndMode:$r, RegF64:$a, f64imm:$b),
> binar...
2011 Oct 07
6
[LLVMdev] Enhancing TableGen
Evan Cheng <evan.cheng at apple.com> writes:
> David, we cannot accept the 'multidef' keyword. Please revert it.
Working on it now.
> We appreciate you thinking ahead about MIC, but we are against the
> massive refactoring and complicated abstraction scheme. We'll never
> accept those patches.
How about a less massive and complicated scheme? I think we can
make
2011 Oct 06
4
[LLVMdev] TableGen and Greenspun
...ing. In this example:
(Equivalent TableGen code with a for-loop)
----------------------------------------
multiclass PTX_FLOAT_4OP<string opcstr, SDNode opnode1, SDNode opnode2> {
for nbit = [32, 32, 64, 64],
op_suffix = [r, i, r, i],
op_type = [RegF32, f32imm, RegF64, f64imm],
op_node_type = [RegF32, fpimm, RegF64, fpimm] in {
def rr#op_suffix#nbit
: InstPTX<(outs RegF#nbit:$d),
(ins RegF#nbit:$a, RegF#nbit:$b, #op_type:$c),
!strconcat(opcstr, ".f#nbit\t$d, $a, $b, $c"),
[(set RegF#nbi...
2011 Oct 08
3
[LLVMdev] Enhancing TableGen
...rn<opcstrm "f32">.pattern, []>;
>> def ri32 : InstPTX<(outs RegF32:$d),
>> (ins RndMode:$r, RegF32:$a, f32imm:$b),
>> binary_pattern<opcstrm "f32">.pattern, []>;
>> def rr64 : InstPTX<(outs RegF64:$d),
>> (ins RndMode:$r, RegF64:$a, RegF64:$b),
>> binary_pattern<opcstrm "f64">.pattern, []>;
>> def ri64 : InstPTX<(outs RegF64:$d),
>> (ins RndMode:$r, RegF64:$a, f64imm:$b),
>> ...
2011 Oct 06
0
[LLVMdev] TableGen and Greenspun
Jakob Stoklund Olesen <jolesen at apple.com> writes:
> The TableGen language seems to be growing Lisp macros from two
> different directions.
>
> Che-Liang Chiou added a preprocessor with for loops, and David Greene
> added multidefs.
>
> It seems that some kind of macro facility is needed, perhaps we should
> discuss what it is supposed to look like?
Don't
2011 Oct 06
3
[LLVMdev] TableGen and Greenspun
The TableGen language seems to be growing Lisp macros from two different directions.
Che-Liang Chiou added a preprocessor with for loops, and David Greene added multidefs.
It seems that some kind of macro facility is needed, perhaps we should discuss what it is supposed to look like?
/jakob
2011 May 13
3
[LLVMdev] [ptx] Propose a register class naming convention change
Hi,
Current register class naming has a confusing prefix letter 'R' (it is
my bad), such as the first 'R' of RRegu32 (for unsigned 32-bit
registers).
I propose a 'Reg' + type name naming convention for register classes; such as:
Regu16, Regu32, Regf32, Regf64
With one exception for predicate registers (capitalized first letter of 'pred'):
RegPred
Since predicate registers are special in the way that they can't be
passed as arguments or load from/store to memory, I think a little
name convention exception for it is okay.
What do you think...
2011 Oct 06
0
[LLVMdev] Enhacing TabelGen
...Equivalent TableGen code with a for-loop)
> ----------------------------------------
> multiclass PTX_FLOAT_4OP<string opcstr, SDNode opnode1, SDNode opnode2> {
> for nbit = [32, 32, 64, 64],
> op_suffix = [r, i, r, i],
> op_type = [RegF32, f32imm, RegF64, f64imm],
> op_node_type = [RegF32, fpimm, RegF64, fpimm] in {
> def !strconcat(!strconcat("rr", !cast<string>(op_suffix)), "nbit")
> [...]
> }
> }
>
> Yes, it's a bit more verbose but also more flexible in what you can do
> wi...
2011 May 13
0
[LLVMdev] [ptx] Propose a register class naming convention change
...Current register class naming has a confusing prefix letter 'R' (it is
> my bad), such as the first 'R' of RRegu32 (for unsigned 32-bit
> registers).
>
> I propose a 'Reg' + type name naming convention for register classes; such as:
> Regu16, Regu32, Regf32, Regf64
> With one exception for predicate registers (capitalized first letter of 'pred'):
> RegPred
>
> Since predicate registers are special in the way that they can't be
> passed as arguments or load from/store to memory, I think a little
> name convention exception for i...
2011 May 13
2
[LLVMdev] [ptx] Propose a register class naming convention change
...g has a confusing prefix letter 'R' (it is
>> my bad), such as the first 'R' of RRegu32 (for unsigned 32-bit
>> registers).
>>
>> I propose a 'Reg' + type name naming convention for register classes; such
>> as:
>> Regu16, Regu32, Regf32, Regf64
>> With one exception for predicate registers (capitalized first letter of
>> 'pred'):
>> RegPred
>>
>> Since predicate registers are special in the way that they can't be
>> passed as arguments or load from/store to memory, I think a little
>>...
2011 May 13
1
[LLVMdev] [ptx] Propose a register class naming convention change
...letter 'R' (it is
>>> my bad), such as the first 'R' of RRegu32 (for unsigned 32-bit
>>> registers).
>>>
>>> I propose a 'Reg' + type name naming convention for register classes;
>>> such as:
>>> Regu16, Regu32, Regf32, Regf64
>>> With one exception for predicate registers (capitalized first letter of
>>> 'pred'):
>>> RegPred
>>>
>>> Since predicate registers are special in the way that they can't be
>>> passed as arguments or load from/store to memory, I...
2011 May 13
0
[LLVMdev] [ptx] Propose a register class naming convention change
...as a confusing prefix letter 'R' (it is<br>
my bad), such as the first 'R' of RRegu32 (for unsigned 32-bit<br>
registers).<br>
<br>
I propose a 'Reg' + type name naming convention for register classes;
such as:<br>
Regu16, Regu32, Regf32, Regf64<br>
With one exception for predicate registers (capitalized first letter of
'pred'):<br>
RegPred<br>
<br>
Since predicate registers are special in the way that they can't be<br>
passed as arguments or load from/store to memory, I think a little<br...
2011 Oct 06
0
[LLVMdev] MIPS 32bit code generation
...ing. In this example:
(Equivalent TableGen code with a for-loop)
----------------------------------------
multiclass PTX_FLOAT_4OP<string opcstr, SDNode opnode1, SDNode opnode2> {
for nbit = [32, 32, 64, 64],
op_suffix = [r, i, r, i],
op_type = [RegF32, f32imm, RegF64, f64imm],
op_node_type = [RegF32, fpimm, RegF64, fpimm] in {
def rr#op_suffix#nbit
: InstPTX<(outs RegF#nbit:$d),
(ins RegF#nbit:$a, RegF#nbit:$b, #op_type:$c),
!strconcat(opcstr, ".f#nbit\t$d, $a, $b, $c"),
[(set RegF#nbi...