Displaying 2 results from an estimated 2 matches for "reg4x32".
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2009 Feb 13
3
[LLVMdev] Modeling GPU vector registers, again (with my implementation)
...and ADD have an 'OptionalDefOperand' writemask. By default the writemask
is
"xyzw" (all elmenets are written).
// 0xF == all elements are written by default
def WRITEMASK : OptionalDefOperand<OtherVT, (ops i32imm), (ops (i32 0xF))>
{...}
def MUL : MyInst<(outs REG4X32:$dst),
(ins REG4X32:$src0, REG4X32:$src1, WRITEMASK:$wm),
In the said post-register-allocation FunctionPass, in addition to replace
the
destination registers as described before, the writemask ($wm) of each
instruction is also replaced with the writemask operands of MERGE. So:...
2009 Feb 13
0
[LLVMdev] Modeling GPU vector registers, again (with my implementation)
...writemask. By default the
> writemask is
> "xyzw" (all elmenets are written).
>
> // 0xF == all elements are written by default
> def WRITEMASK : OptionalDefOperand<OtherVT, (ops i32imm), (ops
> (i32 0xF))>
> {...}
>
> def MUL : MyInst<(outs REG4X32:$dst),
> (ins REG4X32:$src0, REG4X32:$src1, WRITEMASK:$wm),
>
> In the said post-register-allocation FunctionPass, in addition to
> replace the
> destination registers as described before, the writemask ($wm) of each
> instruction is also replaced with the wr...