search for: reg32

This patchset applies some minor fixes to renouveau.xml and then unifies the nv30 and nv40 register definitions. nv30 and nv40 are very similar and have the same offsets for the registers they share. The major differences are: 1. Texture setup is different due to full NPOT support on nv40 2. More advanced blending/render targets on nv40 3. NV30 has fixed function registers, which NV40 lacks The

Hi, This is my work in documenting EVO. I did some RE to fill missing gaps. Best regards, Maxim Levitsky

...a/renouveau.xml +++ b/renouveau.xml @@ -2498,55 +2498,6 @@ <bitfield name="STRIDE" high="15" low="8" type="int"/> <bitfield name="POS_HOMOGENEOUS" high="24" low="24" type="boolean"/> </reg32> - - <reg32 offset="0x0d00" name="VERTEX_ARRAY_OFFSET_POS" type="hexa"/> - <reg32 offset="0x0d04" name="VERTEX_ARRAY_FORMAT_POS" type="bitfield"> - <bitfield name="TYPE" high="3" low="0...

...dex 13b6a7b..e236921 100644 --- a/rnndb/display/nv3_pramdac.xml +++ b/rnndb/display/nv3_pramdac.xml @@ -79,12 +79,79 @@ <bitfield pos="28" name="VCLK_DB2"/> <bitfield pos="29" name="VCLK2_DB2" variants="NV11:NV20 NV25:G80"/> </reg32> + <reg32 offset="0x510" name="PLL_SETUP_CONTROL"/> <reg32 offset="0x520" name="VPLL2" variants="NV11:NV20 NV25:NV30 NV31:G80" type="nv3_pll"/> <reg32 offset="0x520" name="VPLL2" variants="NV3...

...h 1/5 Class 0x0597 Mthd 0x0208 Data 0x01000100:0x00000105 LINEAR + A8R8G8B8 Ch 1/5 Class 0x0597 Mthd 0x0208 Data 0x01000100:0x00000108 Ch 1/5 Class 0x0597 Mthd 0x0208 Data 0x00800080:0x00000108 The only value I found in renouveau dump was 0x00000128. Let's look at renouveau.xml nv20 <reg32 offset="0x0208" name="RT_FORMAT" type="bitfield"> <bitfield name="TYPE" high="11" low="8" type="enum" enum_name="nv40_rendertarget_type"/> <bitfield name="COLOR" high="4" low=...

...t;doc> Refresh to activate delay. </doc> > </bitfield> > <bitfield high="31" low="24" name="RC"> > - <doc> Row cycle time. </doc> > + <doc> Row Cycle time. </doc> > + </bitfield> > + </reg32> > + > + <reg32 offset="0x290" name="MEM_TIMINGS_0" variants="NVC0-"> > + <doc> This, and the next 6 regs, are all related to memtimings. > + A good place to read might be http://www.tweakers.fr/timings.html . > + Most bitfields are u...

Hi, I'm having an issue with subregisters on my target. With a pseudo that writes to a 32 bit reg: %vreg20<def> = toHi16_low0_pseudo %vreg2; reg32:%vreg20 hi16:%vreg2 expands to %vreg2<def> = COPY %a2h; hi16:%vreg2 %vreg43<def> = mov 0, pred:0, pred:%noreg, %ac0<imp-use>, %ac1<imp-use>; lo16:%vreg43 %vreg20<def> = REG_SEQUENCE %vreg2, hi16, %vreg43, lo16; reg32:%vreg20 hi16:%vreg2 lo16:%...

...name="RFC"> <doc> Refresh to activate delay. </doc> </bitfield> <bitfield high="31" low="24" name="RC"> - <doc> Row cycle time. </doc> + <doc> Row Cycle time. </doc> + </bitfield> + </reg32> + + <reg32 offset="0x290" name="MEM_TIMINGS_0" variants="NVC0-"> + <doc> This, and the next 6 regs, are all related to memtimings. + A good place to read might be http://www.tweakers.fr/timings.html . + Most bitfields are unknown. + </doc>...

...lo, I've recently come across an error reported by the GPU and would like to know what it means and especially what causes it to be triggered. Any information would be very useful: I'm seeing MP warp error 0x10 (appears in MP register 0x48). This is what we currently have in nouveau: <reg32 offset="0x048" name="TRAP_WARP_ERROR"> <!-- ctx-switched --> <bitfield high="15" low="0" name="ID"> <value value="1" name="STACK_MISMATCH"/> <value value="5" name="MISALIGNED_PC"/> &...

...support to nouveau for features like atomic counters and images, I'm running into some confusion about what the first word of the shader header means. Here is the definition as we have it today: https://github.com/envytools/envytools/blob/master/rnndb/graph/gf100_shaders.xml VS/HS/DS/GS: <reg32 offset="0" name="0"> <bitfield high="7" low="0" name="MAGIC"> <value value="0x61" name="VP_MAGIC"/> </bitfield> <bitfield high="12" low="10" name="KIND" type="G...

...PU and would like >> to know what it means and especially what causes it to be triggered. >> Any information would be very useful: >> >> I'm seeing MP warp error 0x10 (appears in MP register 0x48). This is >> what we currently have in nouveau: >> >> <reg32 offset="0x048" name="TRAP_WARP_ERROR"> <!-- ctx-switched --> >> <bitfield high="15" low="0" name="ID"> >> <value value="1" name="STACK_MISMATCH"/> >> <value value="5" name=&quot...

Chris Lattner wrote: > On Thu, 2 Dec 2004, Brent Monroe wrote: > >>I'm trying to add the xadd instruction to the X86 back end. >>xadd r/m32, r32 >>exchanges r/m32 and r32, and loads the sum into r/m32. I'm >>interested in the case where the destination operand is a >>memory location. >> >>I've added the following entry to

...-endian mode. Not sure about NV1A, which was the IGP of the series and IIRC logically pre-NV11 as well (but clearly could only be used with x86 chips, since it was part of the motherboard). Aha, it's documented in rnndb: https://github.com/envytools/envytools/blob/master/rnndb/bus/pmc.xml <reg32 offset="0x004" name="ENDIAN" variants="NV1A-"/> -ilia

...know what it means and especially what causes it to be triggered. > >> Any information would be very useful: > >> > >> I'm seeing MP warp error 0x10 (appears in MP register 0x48). This is > >> what we currently have in nouveau: > >> > >> <reg32 offset="0x048" name="TRAP_WARP_ERROR"> <!-- ctx-switched --> > >> <bitfield high="15" low="0" name="ID"> > >> <value value="1" name="STACK_MISMATCH"/> > >> <value value="5&q...

...teve, I will try this out. I hadn’t realised that TableGen was restricted to matching instructions with more than one output operand. I’m assuming that this is only a limitation for inferring an instruction from the patterns, because it does seem to manage schedules okay. Curiously, my memory Reg32+Reg16 pattern is very similar to yours (the 16-bit offset is sign-extended though): // Memory address: 32-bit base register + 16-bit offset register def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", []>; def MEMrr : Operand<iPTR> { let PrintMethod = "printMemO...

...rial at the end of the “Selection DAG Select Phase” in “The LLVM Target-Independent Code Generator”, http://llvm.org/docs/CodeGenerator.html#selectiondag-select-phase. I’ve not actually checked TableGen though so can’t be 100% sure that the documentation is still in date. Curiously, my memory Reg32+Reg16 pattern is very similar to yours (the 16-bit offset is sign-extended though): // Memory address: 32-bit base register + 16-bit offset register def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", []>; def MEMrr : Operand<iPTR> { let PrintMethod = "printMemO...

Dear R list As suggested by Prof Brian Ripley, I have tried to read acf literature. The main problem is I am not the statistician and hence have some problem in understanding the concepts immediately. I came across one literature (http://www.stat.nus.edu.sg/~staxyc/REG32.pdf) on auto-correlation giving the methodology. As per that literature, the auto-correlation is arrived at as per following. y = c(15.91,9.80,17.16,16.68,15.53,22.66,31.01,8.62,45.82,10.97,45.46,28.69,36.75,37.75, 41.18,42.67,46.05, 43.70,53.08,47.56) t = c(1:20) # defining time variable. Fitti...

..., which was the IGP of the series and IIRC > logically pre-NV11 as well (but clearly could only be used with x86 > chips, since it was part of the motherboard). > > Aha, it's documented in rnndb: > > https://github.com/envytools/envytools/blob/master/rnndb/bus/pmc.xml > <reg32 offset="0x004" name="ENDIAN" variants="NV1A-"/> > ohh, I should have checked there.. yeah, will write a fix for it then. Before my patch we just always tried to switch it, but never threw an error. > -ilia >

...nd IIRC > > logically pre-NV11 as well (but clearly could only be used with x86 > > chips, since it was part of the motherboard). > > > > Aha, it's documented in rnndb: > > > > https://github.com/envytools/envytools/blob/master/rnndb/bus/pmc.xml > > <reg32 offset="0x004" name="ENDIAN" variants="NV1A-"/> > > > > ohh, I should have checked there.. yeah, will write a fix for it then. > Before my patch we just always tried to switch it, but never threw an > error. Any progress with the patch? -- Ondr...

https://bugs.freedesktop.org/show_bug.cgi?id=70390 Priority: medium Bug ID: 70390 Assignee: nouveau at lists.freedesktop.org Summary: G84: Repeated system crashes under graphics load, E[PFIFO] DMA_PUSHER and lots of E[PGRAPH] QA Contact: xorg-team at lists.x.org Severity: normal Classification: Unclassified