search for: reg4

...grip$morph<-as.character(grip$Morph) morph<- grip$morph BML<-grip$BML grip$MCF->MCF reg1<-lm(BML~MCF,data=subset(grip,morph=="mel"));reg1 reg2<-lm(BML~MCF,data=subset(grip,morph=="tham"));reg2 reg3<-lm(BML~MCF,data=subset(grip,morph=="A"));reg3 reg4<-lm(BML~MCF,data=subset(grip,morph=="B"));reg4 reg5<-lm(BML~MCF,data=subset(grip,morph=="C"));reg5 plot(MCF,BML,pch=c(2,6,5,19,15)[grip$morph],xlab="Residual Metacarpal Length",ylab="Residual Hand Strength (Broad Dowel)", main="Males") ablin...

...combe<-read.table(fname, header=TRUE) names(anscombe)<-c("x1","y1","x2","y2","x3","y3","x4","y4") reg1<-lm(y1~1 + x1, data=anscombe) reg2<-lm(y2~1 + x2, data=anscombe) reg3<-lm(y3~1 + x3, data=anscombe) reg4<-lm(y4~1 + x4, data=anscombe) summary(reg1) summary(reg2) summary(reg3) summary(reg4) par(mfrow=c(2,2)) plot(x1,y1) abline(reg1) plot(x2,y2) abline(reg2) plot(x3,y3) abline(reg3) plot(x4,y4) abline(reg4) .......................................................................... fname<...

...is defined, other parts of the register are always left untouched - they are neither read or def:ed. It however seems that Codegen treats subregister definitions as somehow clobbering the whole register. The SSA-code looks like this after isel: (Reg0 and Reg1 are 16bit registers. Reg2, Reg3 and Reg4 are 32 bit registers with 16bit subregs, hi16 and lo16.) Reg0 = #imm0 Reg1 = #imm1 Reg2 = IMPLICIT_DEF Reg3 = INSERT_SUBREG Reg2, Reg0, hi16 Reg4 = INSERT_SUBREG Reg3, Reg1, lo16 After TwoAddressInstructionPass it becomes: Reg5:hi16<def,read-undef> = Reg0 Reg5:lo16<def> =...

...fine void @f1() #0 { > -entry: > - store float 0x3FFA76C8C0000000, float* @f, align 4 > - ret void > -; CHECK: .ent f1 > -; CHECK: lui $[[REG1:[0-9]+]], 16339 > -; CHECK: ori $[[REG2:[0-9]+]], $[[REG1]], 46662 > -; CHECK: mtc1 $[[REG2]], $f[[REG3:[0-9]+]] > -; CHECK: lw $[[REG4:[0-9]+]], %got(f)(${{[0-9]+}}) > -; CHECK: swc1 $f[[REG3]], 0($[[REG4]]) > -; CHECK: .end f1 > - > -} > - > -; Function Attrs: nounwind > -define void @d1() #0 { > -entry: > - store double 1.234567e+00, double* @de, align 8 > -; CHECK: .ent d1 > -; CHECK: lui $[[R...

...+; LIN: movaps (%rsi), %xmm0 >> +; LIN: andps (%rdx), %xmm0 >> +; LIN: movaps %xmm0, -24(%rsp) >> +; LIN: movslq -24(%rsp), %[[REG1:r.+]] >> +; LIN: movslq -20(%rsp), %[[REG2:r.+]] >> +; LIN: movslq -16(%rsp), %[[REG3:r.+]] >> +; LIN: movslq -12(%rsp), %[[REG4:r.+]] >> +; LIN: movsd (%rdi,%[[REG1]],8), %xmm0 >> +; LIN: movhpd (%rdi,%[[REG2]],8), %xmm0 >> +; LIN: movsd (%rdi,%[[REG3]],8), %xmm1 >> +; LIN: movhpd (%rdi,%[[REG4]],8), %xmm1 >> + >> +; WIN: movaps (%rdx), %xmm0 >> +; WIN: andps (%r8), %xmm0 &...

Hello everyone, this is the fourth version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See

Hello everyone, this is the very first version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See