Displaying 20 results from an estimated 33 matches for "reg3".
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2015 Feb 27
2
[LLVMdev] LLVM register number for MIPS DAGToDAG
Is it possible to get a register number to which the value is allocated to
in MIPS in DAGToDAG class?
More Specifically:
SDValue Reg3 = Node->getOperand(3);
if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Reg3))
{
op3 = cast<RegisterSDNode>(Reg3)->getReg();
fprintf(stderr,"Op3 is register and regnum is
%d\n",op3);...
2015 Feb 27
0
[LLVMdev] LLVM register number for MIPS DAGToDAG
> On Feb 27, 2015, at 1:59 AM, Ambuj Agrawal <ambujbwt at gmail.com> wrote:
>
> Is it possible to get a register number to which the value is allocated to in MIPS in DAGToDAG class?
>
> More Specifically:
> SDValue Reg3 = Node->getOperand(3);
> if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Reg3))
> {
> op3 = cast<RegisterSDNode>(Reg3)->getReg();
> fprintf(stderr,"Op3 is register and regn...
2015 Feb 28
2
[LLVMdev] LLVM register number for MIPS DAGToDAG
...>
> > On Feb 27, 2015, at 1:59 AM, Ambuj Agrawal <ambujbwt at gmail.com> wrote:
> >
> > Is it possible to get a register number to which the value is allocated
> to in MIPS in DAGToDAG class?
> >
> > More Specifically:
> > SDValue Reg3 = Node->getOperand(3);
> > if (RegisterSDNode *R =
> dyn_cast<RegisterSDNode>(Reg3))
> > {
> > op3 = cast<RegisterSDNode>(Reg3)->getReg();
> > fprintf(stderr,"Op...
2007 Oct 09
2
fit.contrast and interaction terms
...ith Y as response variable and X a categorical variable (with 4 categories), with the aim of comparing the basal category of X (category=1) with category 4. Unfortunately, there is another categorical variable with 2 categories which interact with x and I have to include it, so my model is s "reg3: Y=x*x3". Using fit.contrast to make the contrast (category 1 vs category 4) with options(contrasts=c("contr.treatment", "contr.poly")), it makes the contrast but just for the basal category of x3, (coincident with the corresponding result of summary(reg3)), so that it is n...
2008 Aug 13
2
which alternative tests instead of AIC/BIC for choosing models
...o AIC or BIC to choose model parameters.
This is somewhat of a general statistics question, but I ask it in this
forum as I am looking for a R solution.
Suppose I have one dependent variable, y, and two independent variables,
x1 an x2.
I can perform three regressions:
reg1: y~x1
reg2: y~x2
reg3: y~x1+x2
The AIC of reg1 is 2000, reg2 is 1000 and reg3 is 950. One would,
presumably, conclude that one should use both x1 and x2. However, the
R^2's are quite different: R^2 of reg1 is 0.5%, reg2 is 95% and reg3 is
95.25%. Knowing that, I would actually conclude that x1 adds litte and...
2016 May 09
2
Replacing an instruction in a post-RA pass
...|| isLoadRR(opcode)){
MachineBasicBlock& MBB = *MFI;
MachineInstr& MI = *II;
DebugLoc DL = MI.getDebugLoc();
MachineOperand& reg1 = MI.getOperand(0);
MachineOperand& reg2 = MI.getOperand(1);
MachineOperand& reg3 = MI.getOperand(2);
if(reg1.isReg() && reg2.isReg() && reg3.isReg()){
if((reg1.getReg()-8)%4 == (reg3.getReg()-8)%4){
MachineBasicBlock::instr_iterator NII = std::next(II);
//conflict if reg1 and reg3 are in same bank...
2017 Sep 14
2
Live Register Spilling
...ctually working on MIPS backend to generate smaller set of MIPS Instructions compared to its existing supported instructions.
> Currently, i am working on shifting instructions.
>
> Take an example:
> A typical mips sllv syntax goes in this manner:
>
> sllv $reg1,$reg2,$reg3
>
> The $reg3 contains the shifting amount. Only the LSB 5 bit will be used.
> The $reg2 contains the data to be shifted.
> The $reg1 contains the data after shifting is performed.
>
> What i want to achieve is to expand sllv instruction to the following routine:
>
>...
2012 Sep 28
1
blank plot----how do I make symbols appear
...csv("grip.csv")->grip
grip
class(grip)
class(HAND)
grip$morph<-as.character(grip$Morph)
morph<- grip$morph
BML<-grip$BML
grip$MCF->MCF
reg1<-lm(BML~MCF,data=subset(grip,morph=="mel"));reg1
reg2<-lm(BML~MCF,data=subset(grip,morph=="tham"));reg2
reg3<-lm(BML~MCF,data=subset(grip,morph=="A"));reg3
reg4<-lm(BML~MCF,data=subset(grip,morph=="B"));reg4
reg5<-lm(BML~MCF,data=subset(grip,morph=="C"));reg5
plot(MCF,BML,pch=c(2,6,5,19,15)[grip$morph],xlab="Residual Metacarpal
Length",ylab="Residual...
2017 Feb 14
2
Ensuring chain dependencies with expansion to libcalls
...snippet of a DAG demonstrates the problem.
t0: ch = EntryToken
t2: i64,ch,glue = CopyFromReg t0, Register:i64 %reg0
t4: i64,ch,glue = CopyFromReg t2:1, Register:i64 %reg1, t2:1
t6: i64,ch,glue = CopyFromReg t4:1, Register:i64 %reg2, t4:1
t8: i64,ch,glue = CopyFromReg t6:1, Register:i64 %reg3, t6:1
t11: ch = CopyToReg t0, Register:i64 %vreg0, t2
t13: ch = CopyToReg t0, Register:i64 %vreg1, t4
t15: ch = CopyToReg t0, Register:i64 %vreg2, t8
t26: ch = TokenFactor t11, t13, t15, t2:1, t4:1, t6:1, t8:1
t16: i64 = sdiv t2, t4
Before legalization, there is...
2007 Dec 05
1
Working with "ts" objects
...u
Phone: 334 844-2922
anscombe<-read.table(fname, header=TRUE)
names(anscombe)<-c("x1","y1","x2","y2","x3","y3","x4","y4")
reg1<-lm(y1~1 + x1, data=anscombe)
reg2<-lm(y2~1 + x2, data=anscombe)
reg3<-lm(y3~1 + x3, data=anscombe)
reg4<-lm(y4~1 + x4, data=anscombe)
summary(reg1)
summary(reg2)
summary(reg3)
summary(reg4)
par(mfrow=c(2,2))
plot(x1,y1)
abline(reg1)
plot(x2,y2)
abline(reg2)
plot(x3,y3)
abline(reg3)
plot(x4,y4)
abline(reg4)
.................................................
2009 Aug 16
1
How to deal with multicollinearity in mixed models (with lmer)?
Dear R users,
I have a problem with multicollinearity in mixed models and I am using lmer
in package lme4. From previous mailing list, I learn of a reply
"http://www.mail-archive.com/r-help at stat.math.ethz.ch/msg38537.html" which
states that if not for interpretation but just for prediction,
multicollinearity does not matter much. However, I am using mixed model to
interpret something,
2014 Aug 15
2
[LLVMdev] Help with definition of subregisters; spill, rematerialization and implicit uses
...bregister is defined, other parts of the register
are always left untouched - they are neither read or def:ed.
It however seems that Codegen treats subregister definitions as somehow
clobbering the whole register.
The SSA-code looks like this after isel:
(Reg0 and Reg1 are 16bit registers. Reg2, Reg3 and Reg4 are 32 bit
registers with 16bit subregs, hi16 and lo16.)
Reg0 = #imm0
Reg1 = #imm1
Reg2 = IMPLICIT_DEF
Reg3 = INSERT_SUBREG Reg2, Reg0, hi16
Reg4 = INSERT_SUBREG Reg3, Reg1, lo16
After TwoAddressInstructionPass it becomes:
Reg5:hi16<def,read-undef> = Reg0
Reg5:lo16<def>...
2017 Sep 12
2
Live Register Spilling
Running llc with '-verify-machineinstrs' may tell you which instruction break the SSA form.
Ruiling
From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of jin chuan see via llvm-dev
Sent: Monday, September 11, 2017 10:02 AM
To: Matthias Braun <mbraun at apple.com>
Cc: llvm-dev at lists.llvm.org
Subject: Re: [llvm-dev] Live Register Spilling
Sorry about the
2009 Jan 19
0
[LLVMdev] HazardRecognizer and RegisterAllocation
On Jan 19, 2009, at 9:17 AM, Patrick Boettcher wrote:
> Hi list,
>
> in our LLVM-based-project we are writing a backend for our
> processor. The
> architecture is a quite straight-forward RISC, but it does not have
> hardware interlocks, i.e. data hazards involving memory access must be
> resolved by the compiler, either by scheduling unrelated
> instructions or
>
2009 Jan 19
3
[LLVMdev] HazardRecognizer and RegisterAllocation
...only 3 registers available the
code post-hazard-recognized looks like that:
load 0x1234, reg1024
load 0x1236, reg1025
load 0x1238, reg1026
load 0x1240, reg1027
add reg1024, 1
add reg1025, 2
add reg1026, 3
add reg1027, 4
after register allocation:
load 0x1234, reg1
load 0x1236, reg2
load 0x1238, reg3
add reg1, 1
add reg2, 2
add reg3, 3
store reg1, 0x1234
load 0x1240, reg1
add reg1, 4
Which won't work on our platform. It is missing 2 NOOPs after the last
load. The DelaySlotFiller could add the two NOOPs, but that would be less
optimal than doing the store-load before the add of reg2 and r...
2009 Jan 19
2
[LLVMdev] HazardRecognizer and RegisterAllocation
Hi list,
in our LLVM-based-project we are writing a backend for our processor. The
architecture is a quite straight-forward RISC, but it does not have
hardware interlocks, i.e. data hazards involving memory access must be
resolved by the compiler, either by scheduling unrelated instructions or
by inserting NOOPs into the load delay slots:
----
For example, code which looks like that:
load
2013 Nov 19
2
[LLVMdev] [3.4 branch] PPC64 regressions
...enSUSE 13.1
PPC64.
Total of 3 failures which seems to be due the same problem (the value in
brackets is the time counter from the build system):
[ 3468s]
/home/abuild/rpmbuild/BUILD/llvm/test/CodeGen/PowerPC/ppc32-vacopy.ll:21:10:
error: expected string not found in input
[ 3468s] ; CHECK: lwz [[REG3:[0-9]+]], {{.*}}
[ 3468s] ^
[ 3468s] <stdin>:15:2: note: scanning from here
[ 3468s] stw 5, 16(1)
[ 3468s] ^
[ 3468s] <stdin>:17:3: note: possible intended match here
[ 3468s] stw 4, 4(7)
[ 3468s] ^
[ 3467s]
/home/abuild/rpmbuild/BUILD/llvm/test/CodeGen/PowerPC/anon_aggr....
2008 Mar 20
0
[RFC/PATCH 07/15] kvm-s390: interrupt subsystem, cpu timer, waitpsw
.../kvm/intercept.c
+++ kvm/arch/s390/kvm/intercept.c
@@ -18,6 +18,91 @@
#include <asm/kvm_host.h>
#include "kvm-s390.h"
+#include "gaccess.h"
+
+static int handle_lctg(struct kvm_vcpu *vcpu)
+{
+ int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4;
+ int reg3 = vcpu->arch.sie_block->ipa & 0x000f;
+ int base2 = vcpu->arch.sie_block->ipb >> 28;
+ int disp2 = ((vcpu->arch.sie_block->ipb & 0x0fff0000) >> 16) +
+ ((vcpu->arch.sie_block->ipb & 0xff00) << 4);
+ u64 useraddr;
+ int reg, rc;
+
+ vcpu->st...
2009 Nov 24
2
random effects correlation in lmer
I am having an issue with lmer that I wonder if someone could explain.
I am trying to fit a mixed effects model to a set of longitudinal data
over a set of individual subjects:
(fm1 <- lmer(x ~ time + (time|ID),aa))
I quite often find that the correlation between the random effects is 1.0:
Linear mixed model fit by REML
Formula: x ~ time + (time | ID)
Data: aa
AIC BIC logLik deviance
2013 Nov 19
0
[LLVMdev] [3.4 branch] PPC64 regressions
...eems to be due the same problem (the value
> in brackets is the time counter from the build system):
>
>
>
>
> [ 3468s]
> /home/abuild/rpmbuild/BUILD/llvm/test/CodeGen/PowerPC/ppc32-vacopy.ll:21:10:
> error: expected string not found in input
> [ 3468s] ; CHECK: lwz [[REG3:[0-9]+]], {{.*}}
> [ 3468s] ^
> [ 3468s] <stdin>:15:2: note: scanning from here
> [ 3468s] stw 5, 16(1)
> [ 3468s] ^
> [ 3468s] <stdin>:17:3: note: possible intended match here
> [ 3468s] stw 4, 4(7)
> [ 3468s] ^
>
>
>
> [ 3467s]
> /home/abuild/rpm...