search for: reg2

We have a test that looks like this… define void @array16_store() { ; CHECK-LABEL: array16_store: ; CHECK: ldi [[REG1:r[0-9]+]], 204 ; CHECK: ldi [[REG2:r[0-9]+]], 170 ; CHECK: sts int.array+3, [[REG2]] ; CHECK: sts int.array+2, [[REG1]] ; CHECK: ldi [[REG1:r[0-9]+]], 187 ; CHECK: ldi [[REG2:r[0-9]+]], 170 ; CHECK: sts int.array+1, [[REG2]] ; CHECK: sts int.array, [[REG1]] ; CHECK: ldi [[REG1:r[0-9]+]], 221 ; CHECK: ldi [[REG2:r[0-9]+]], 170 ; C...

...p(1:20) n<-c(10,20,13,22,28,12,12,36,19,12,36,75,33,121,37,14,40,16,14,20) r<-c(.68,.56,.23,.64,.49,-.04,.49,.33,.58,.18,-.11,.27,.26,.40,.49, .51,.40,.34,.42,.16) mod2<-factor(c(rep(c(1,2,3,4),5))) da<-data.frame(id, n, r, mod1, mod2) reg0<-lm(da$r ~ 1) reg1<-lm(da$r ~ da$mod1) reg2<-lm(da$r ~ da$mod1 + da$mod2) # This is as far as I get with the function: MRfit <- function( ...) { models <- list(...) fit<- anova(models) return(fit) } MRfit(reg0,reg1,reg2) # This is what I get from R: # Error in UseMethod("anova") : # no applicable method for ...

...ator, the code is identical when compiling with and without -g (with the exception of " DBG_VALUE" instructions). The only difference I can see is the value assigned to the slot index for each instruction. As an example, without -g a snippet of a basic block looks like this: 32B %vreg29<def> = LDImm 1; REG1:%vreg29 36B %vreg44<def> = LDImm 1103515245; REG1:%vreg44 40B %vreg143:vsub32_1<def,read-undef> = LDImm 0; REG2:%vreg143 44B %vreg68<def> = LDImm 12345; REG1:%vreg68 64B %vreg143:vsub32_0<def> = COPY %vreg143:vsub32_1;...

...:45 AM Carl Peto via llvm-dev > <llvm-dev at lists.llvm.org> wrote: >> >> We have a test that looks like this… >> >> define void @array16_store() { >> ; CHECK-LABEL: array16_store: >> >> ; CHECK: ldi [[REG1:r[0-9]+]], 204 >> ; CHECK: ldi [[REG2:r[0-9]+]], 170 >> ; CHECK: sts int.array+3, [[REG2]] >> ; CHECK: sts int.array+2, [[REG1]] >> >> ; CHECK: ldi [[REG1:r[0-9]+]], 187 >> ; CHECK: ldi [[REG2:r[0-9]+]], 170 >> ; CHECK: sts int.array+1, [[REG2]] >> ; CHECK: sts int.array, [[REG1]] >> &g...

...y 4 is done for the intercept, that is, for the numerical variable assumed to be 0. As i am interested in comparing category 1 vs category 4 adjusting for x2 in general terms, I use contr.sum as before, but it does not seem to produce any modification: x2 <- rnorm(100,mean=y,sd=0.5) # NUMERIC reg2 <- lm(y ~ x * x2 ) summary(reg2) # category 1 vs category 4 estimate: 3.067346 for x2=0 options(contrasts=c("contr.treatment", "contr.poly")) fit.contrast(reg2,x,c(-1,0,0,1)) # g4 vs g1 estimate: 3.067346 for x2=0 options(contrasts=c("contr.sum", "contr.po...

...have hardware interlocks, i.e. data hazards involving memory access must be resolved by the compiler, either by scheduling unrelated instructions or by inserting NOOPs into the load delay slots: ---- For example, code which looks like that: load 0x1234, reg1 noop noop add reg1, 1 load 0x1236, reg2 can be safely transformed to: load 0x1234, reg1 load 0x1236, reg2 noop add reg1, 1 ---- It pleased us quite a lot when we found the HazardRecognizer-class. Without much effort we could assist LLVM to transform code like shown above (with simple (SDUse, delayCount)-map). Unfortunately we found...

Each of the data sets contains monthly observations on price indices for 7 countries. I use the fitted values from reg1 in the reg2 model. The interior loop executes without error as long as I explicitly specify the data set, i.e. data=dat70. However the code fails to execute if I specify the model in the form of the commented line, i. e reg1 <-dynlm(form1,data=Dnames[j]) I get the following error message: Error in merge...

...access must be > resolved by the compiler, either by scheduling unrelated > instructions or > by inserting NOOPs into the load delay slots: > > ---- > > For example, code which looks like that: > > load 0x1234, reg1 > noop > noop > add reg1, 1 > load 0x1236, reg2 > > can be safely transformed to: > > load 0x1234, reg1 > load 0x1236, reg2 > noop > add reg1, 1 > > ---- > > It pleased us quite a lot when we found the HazardRecognizer-class. > Without much effort we could assist LLVM to transform code like shown > above (w...

Hello, I'm writing a backend for an architecture that only has LOAD Instructions that first copy the old value of the target register in another register and after that load the provided value into the register. Example of an addition: load a, reg1; // -> copies old value of reg1 in reg2 and loads value from a into reg1 load b, reg1; // -> copies old value of reg1 in reg2 and loads value from b into reg1 add reg1, reg2; // adds values from a and b and saves the result into reg1 So I need to describe the "load X, reg1" Instruction so that LLVM understands it correctly....

...code is identical when compiling with and without -g (with the exception of "DBG_VALUE" instructions). The only difference I can see is the value assigned to the slot index for each instruction. As an example, without -g a snippet of a basic block looks like this: > > 32B %vreg29<def> = LDImm 1; REG1:%vreg29 > 36B %vreg44<def> = LDImm 1103515245; REG1:%vreg44 > 40B %vreg143:vsub32_1<def,read-undef> = LDImm 0; REG2:%vreg143 > 44B %vreg68<def> = LDImm 12345; REG1:%vreg68 > 64B %vreg143:vsub32_0<def> = COPY...

...code is identical when compiling with and without -g (with the exception of "DBG_VALUE" instructions). The only difference I can see is the value assigned to the slot index for each instruction. As an example, without -g a snippet of a basic block looks like this: > > 32B %vreg29<def> = LDImm 1; REG1:%vreg29 > 36B %vreg44<def> = LDImm 1103515245; REG1:%vreg44 > 40B %vreg143:vsub32_1<def,read-undef> = LDImm 0; REG2:%vreg143 > 44B %vreg68<def> = LDImm 12345; REG1:%vreg68 > 64B %vreg143:vsub32_0<def> = COPY...

...lternative to AIC or BIC to choose model parameters. This is somewhat of a general statistics question, but I ask it in this forum as I am looking for a R solution. Suppose I have one dependent variable, y, and two independent variables, x1 an x2. I can perform three regressions: reg1: y~x1 reg2: y~x2 reg3: y~x1+x2 The AIC of reg1 is 2000, reg2 is 1000 and reg3 is 950. One would, presumably, conclude that one should use both x1 and x2. However, the R^2's are quite different: R^2 of reg1 is 0.5%, reg2 is 95% and reg3 is 95.25%. Knowing that, I would actually conclude that x1 adds...

...(Intercept) 0.401 0.633 number of obs: 609, groups: gen, 24; popu, 9; rack, 2 Estimated scale (compare to 1) 0.80656 Fixed effects: Estimate Std. Error z value Pr(>|z|) (Intercept) 2.391 0.574 4.17 3.1e-05 reg1 0.842 0.452 1.86 0.06252 reg2 0.800 0.241 3.32 0.00091 nutrient1 0.788 0.197 4.00 6.3e-05 amd1 -0.540 0.139 -3.88 0.00010 reg1:nutrient1 0.500 0.227 2.21 0.02734 reg2:nutrient1 -0.176 0.146 -1.21 0.22794 Correlation of Fixed Effects:...

To generate code for a target which doesn't have immediate constant as instruction operand, do I (the target specific back-end, XXXTarget) need to provide code to break up the SDNode with constant (like ISD::ADD $reg1, #1) to 2 SDNodes (ISD::LOAD $reg2, #1; ISD::ADD $reg1, $reg2) in my XXXTargetLowering::LowerOperation, or LLVM target-independent framework can do such transformation automatically with my instruction pattern definition? Thanks -Thomson -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://list...

...na.omit(HAND)->HAND write.csv(HAND, "grip.csv") read.csv("grip.csv")->grip grip class(grip) class(HAND) grip$morph<-as.character(grip$Morph) morph<- grip$morph BML<-grip$BML grip$MCF->MCF reg1<-lm(BML~MCF,data=subset(grip,morph=="mel"));reg1 reg2<-lm(BML~MCF,data=subset(grip,morph=="tham"));reg2 reg3<-lm(BML~MCF,data=subset(grip,morph=="A"));reg3 reg4<-lm(BML~MCF,data=subset(grip,morph=="B"));reg4 reg5<-lm(BML~MCF,data=subset(grip,morph=="C"));reg5 plot(MCF,BML,pch=c(2,6,5,19,15)[grip$mo...

Hello, This is a question motivated by curiosity, not a pressing problem. Any responses are much appreciated! In the following code, function reg1 calls glm with a formula object while reg2 uses a string. In both cases, glm works; however, in the second case, the add1 function fails with the following message: "Error in eval(predvars, data, env) : invalid 'envir' argument." Any insight into what is going on "under the hood"? Many thanks, --Krishna x1 =...

...ities are above 1. Is that a problem with my model? I thought the predicted prob can't be bigger than 1... Any help would be really appreciated! Thanks! K. reg1<-glm(pyea~male+edu+married+inc+relig+factor(time)+ factor(time)*male, data=mydata, family=binomial(link="logit")) reg2<-predict.glm(reg1, se.fit=T, data.frame(male=1, edu=1, married=1,inc=1, relig=1, type='response', YEAR=seq(1,33,1)) reg2$fit $fit 1 2 3 4 5 6 7 8 9 10 11 0.6105101 0.5249279 0.4717028 0.5525786 0.562...

Hi everyone, Running the vif() function from the car package like ---------------------------------------------------- > reg2 <- lm(CARsPur~Delay_max10+LawChange+MarketTrend_20d+MultiTrade, data=data.frame(VarVecPur)) > vif(reg2) Delay_max10 LawChange MarketTrend_20d MultiTrade 1.010572 1.009874 1.004278 1.003351 ---------------------------------------------------- giv...

...I am actually working on MIPS backend to generate smaller set of MIPS Instructions compared to its existing supported instructions. > Currently, i am working on shifting instructions. > > Take an example: > A typical mips sllv syntax goes in this manner: > > sllv $reg1,$reg2,$reg3 > > The $reg3 contains the shifting amount. Only the LSB 5 bit will be used. > The $reg2 contains the data to be shifted. > The $reg1 contains the data after shifting is performed. > > What i want to achieve is to expand sllv instruction to the following routine: > &gt...

...ordering in relation to other chains in the DAG. The following snippet of a DAG demonstrates the problem. t0: ch = EntryToken t2: i64,ch,glue = CopyFromReg t0, Register:i64 %reg0 t4: i64,ch,glue = CopyFromReg t2:1, Register:i64 %reg1, t2:1 t6: i64,ch,glue = CopyFromReg t4:1, Register:i64 %reg2, t4:1 t8: i64,ch,glue = CopyFromReg t6:1, Register:i64 %reg3, t6:1 t11: ch = CopyToReg t0, Register:i64 %vreg0, t2 t13: ch = CopyToReg t0, Register:i64 %vreg1, t4 t15: ch = CopyToReg t0, Register:i64 %vreg2, t8 t26: ch = TokenFactor t11, t13, t15, t2:1, t4:1, t6:1, t...