search for: reg16387

...output ends up very wrong, despite the Machine code being initially correct: # Machine code for function func: Function Live Ins: %R0 in reg%16384, %R1 in reg%16385, %R2 in reg%16386, %R3 in reg%16387 Function Live Outs: %R0 BB#0: derived from LLVM BB %entry Live Ins: %R0 %R1 %R2 %R3 %reg16387<def> = COPY %R3; IntRegs:%reg16387 %reg16386<def> = COPY %R2; IntRegs:%reg16386 %reg16385<def> = COPY %R1; IntRegs:%reg16385 %reg16384<def> = COPY %R0; IntRegs:%reg16384 %reg16390<def> = MOVE %reg16386; IntRegs:%reg16390,16386 %r...

...ot; define arm_aapcscc i64 @foo(i64 %a, i64 %b) nounwind readnone { entry: %xor = xor i64 %a, 18 ; <i64> [#uses=1] %xor2 = xor i64 %xor, %b ; <i64> [#uses=1] ret i64 %xor2 } produces these instructions before coalescing: 4L %reg16387<def> = COPY %R3<kill> 12L %reg16386<def> = COPY %R2<kill> 28L %reg16384<def> = COPY %R0<kill> 36L %reg16388<def> = COPY %reg16385<kill> 44L %reg16388<def>, %CPSR<def,dead> = tEOR %reg16388, %reg16387<kill>, pred:14, p...

On Sat, Sep 4, 2010 at 1:31 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > > On Sep 4, 2010, at 11:21 AM, Borja Ferrer wrote: > >> I've noticed this pattern happening with other operators aswell, but used xor in this example. As i said before, i tried with different register allocation orders, but it will produce always the same result. GCC is emitting longer

On Sep 4, 2010, at 11:21 AM, Borja Ferrer wrote: > I've noticed this pattern happening with other operators aswell, but used xor in this example. As i said before, i tried with different register allocation orders, but it will produce always the same result. GCC is emitting longer code, but since LLVM is so nearer to the optimal code sequence i wanted to reach it. In LLVM, copies are

...: Function Live Ins: %R25R24 in reg%16384, %R23R22 in reg%16385 Function Live Outs: %R25R24 BB#0: derived from LLVM BB %entry Live Ins: %R25R24 %R23R22 %reg16385<def> = COPY %R23R22; WDREGS:%reg16385 // COPY B %reg16384<def> = COPY %R25R24; WDREGS:%reg16384 // COPY A %reg16387<def> = COPY %reg16384:ssub_0; GPR8:%reg16387 WDREGS:%reg16384 // EXTRACT LO BYTE OF A %reg16388<def> = COPY %reg16385:ssub_0; GPR8:%reg16388 WDREGS:%reg16385 // EXTRACT LO BYTE OF B %reg16389<def> = COPY %reg16384:ssub_1; GPR8:%reg16389 WDREGS:%reg16384 // EXTRACT HI BYTE...

...ch, I also tried to do a custom InstrInserter that ended with the correct code just after MI emission: 68 %reg16392<def> = LDWr %reg16384<kill>, 0; mem:LD4[<unknown>] 76 %reg16393<def> = LDWr %reg16386<kill>, 0; mem:LD4[<unknown>] 84 %reg16394<def> = LDWr %reg16387<kill>, 0; mem:LD4[<unknown>] 92 %reg16395<def> = LDWr %reg16388<kill>, 0; mem:LD4[<unknown>] 132 %reg16400:1<def,dead> = MOVI32rr %reg16392<kill> 140 %reg16400:2<def> = MOVI32rr %reg16393<kill> 148 %reg16400:3<def> = MOVI32rr %reg16394<...

...70e260 [ID=14] 0x16d5748: ch = EntryToken [ORD=1] [ID=0] 0x170e260: i16 = Register %reg16390 [ID=4] 0x170ed00: ch = seteq [ORD=1] [ID=9] 0x170dc60: i16,ch = CopyFromReg 0x16d5748, 0x170db60 [ORD=1] [ID=11] 0x16d5748: ch = EntryToken [ORD=1] [ID=0] 0x170db60: i16 = Register %reg16387 [ORD=1] [ID=1] 0x170ec00: i16 = Constant<0> [ORD=1] [ID=8] 0x170ef00: ch = BasicBlock<bb1 0x170a5d8> [ID=10] In my InstrInfo.td file I'm trying to match BRCOND as follows: let isBranch = 1 in def CondBranch : F3_1<2, 0b000101, (outs), (ins IntRegs:$L, i1...

...%reg16391:sub_16bit<kill>; GR16:%reg16384 GR32:%reg16391 Successors according to CFG: BB#1 BB#1: derived from LLVM BB %bb Predecessors according to CFG: BB#0 BB#1 %reg16386<def> = PHI %reg16385, <BB#0>, %reg16394, <BB#1>; GR16:%reg16386,16385,16394 %reg16387<def> = PHI %reg16384, <BB#0>, %reg16398, <BB#1>; GR16:%reg16387,16384,16398 %reg16393<def> = MOV16ri 1; GR16:%reg16393 %reg16398<def> = COPY %reg16387; GR16:%reg16398,16387 %reg16398<def> = XOR16rr %reg16398, %reg16386, %EFLAGS<imp-def&...

...custom InstrInserter that > ended with the correct code just after MI emission: > > 68 %reg16392<def> = LDWr %reg16384<kill>, 0; mem:LD4[<unknown>] > 76 %reg16393<def> = LDWr %reg16386<kill>, 0; mem:LD4[<unknown>] > 84 %reg16394<def> = LDWr %reg16387<kill>, 0; mem:LD4[<unknown>] > 92 %reg16395<def> = LDWr %reg16388<kill>, 0; mem:LD4[<unknown>] > 132 %reg16400:1<def,dead> = MOVI32rr %reg16392<kill> > 140 %reg16400:2<def> = MOVI32rr %reg16393<kill> > 148 %reg16400:3<def> = MO...