search for: reg16384

...:$op1, I32Regs:$op2))]>; But then I end up having the following bug: Code %0 = zext i8 %data to i32 %1 = zext i16 %crc to i32 %2 = xor i32 %1, %0 %3 = and i32 %2, 1 %4 = icmp eq i32 %3, 0 which compares the lowest bits of the 2 variables ends up being compiled as %reg16384<def> = LDWi <fi#-2>, 0; mem:LD4[FixedStack-2] I32Regs:%reg16384 %reg16385<def> = LDWi <fi#-1>, 0; mem:LD4[FixedStack-1] I32Regs:%reg16385 %reg16386<def> = COPY %reg16384; I32Regs:%reg16386,16384 %reg16390<def> = NErrb %reg16384, %reg16385;...

...gt; Code > > > %0 = zext i8 %data to i32 > %1 = zext i16 %crc to i32 > %2 = xor i32 %1, %0 > %3 = and i32 %2, 1 > %4 = icmp eq i32 %3, 0 > > > which compares the lowest bits of the 2 variables > > > ends up being compiled as > > > %reg16384<def> = LDWi <fi#-2>, 0; mem:LD4[FixedStack-2] I32Regs:%reg16384 > %reg16385<def> = LDWi <fi#-1>, 0; mem:LD4[FixedStack-1] I32Regs:%reg16385 > %reg16386<def> = COPY %reg16384; I32Regs:%reg16386,16384 > %reg16390<def> = NErrb %reg16384...

...rm16 <fi#-2>, 1, %reg0, 0, %reg0; mem:LD2[FixedStack-2] GR32:%reg16390 %reg16385<def> = COPY %reg16390:sub_16bit<kill>; GR16:%reg16385 GR32:%reg16390 %reg16391<def> = MOVZX32rm16 <fi#-1>, 1, %reg0, 0, %reg0; mem:LD2[FixedStack-1] GR32:%reg16391 %reg16384<def> = COPY %reg16391:sub_16bit<kill>; GR16:%reg16384 GR32:%reg16391 Successors according to CFG: BB#1 ... 2: BB#0: derived from LLVM BB %entry %EDX<def> = MOVZX32rm16 <fi#-2>, 1, %reg0, 0, %reg0; mem:LD2[FixedStack-2] %CX<def> = COPY %EDX...

...>> >> %0 = zext i8 %data to i32 >> %1 = zext i16 %crc to i32 >> %2 = xor i32 %1, %0 >> %3 = and i32 %2, 1 >> %4 = icmp eq i32 %3, 0 >> >> which compares the lowest bits of the 2 variables >> ends up being compiled as >> >> %reg16384<def> = LDWi <fi#-2>, 0; mem:LD4[FixedStack-2] I32Regs:%reg16384 >> %reg16385<def> = LDWi <fi#-1>, 0; mem:LD4[FixedStack-1] I32Regs:%reg16385 >> %reg16386<def> = COPY %reg16384; I32Regs:%reg16386,16384 >> %reg16390<def> = NErrb...

...%16386, %R3 in reg%16387 Function Live Outs: %R0 BB#0: derived from LLVM BB %entry Live Ins: %R0 %R1 %R2 %R3 %reg16387<def> = COPY %R3; IntRegs:%reg16387 %reg16386<def> = COPY %R2; IntRegs:%reg16386 %reg16385<def> = COPY %R1; IntRegs:%reg16385 %reg16384<def> = COPY %R0; IntRegs:%reg16384 %reg16390<def> = MOVE %reg16386; IntRegs:%reg16390,16386 %reg16388<def> = CMPrr %reg16384, %reg16385, %CFR<imp-def,dead>; IntRegs:%reg16388,16384,16385 SKIPCOND 1, %CFR<imp-use> Successors according to CFG:...

...data to i32 >>> %1 = zext i16 %crc to i32 >>> %2 = xor i32 %1, %0 >>> %3 = and i32 %2, 1 >>> %4 = icmp eq i32 %3, 0 >>> >>> which compares the lowest bits of the 2 variables >>> ends up being compiled as >>> >>> %reg16384<def> = LDWi <fi#-2>, 0; mem:LD4[FixedStack-2] I32Regs:%reg16384 >>> %reg16385<def> = LDWi <fi#-1>, 0; mem:LD4[FixedStack-1] I32Regs:%reg16385 >>> %reg16386<def> = COPY %reg16384; I32Regs:%reg16386,16384 >>> %reg16390<def&...

...>> %2 = xor i32 %1, %0 >>>>> %3 = and i32 %2, 1 >>>>> %4 = icmp eq i32 %3, 0 >>>>> >>>>> which compares the lowest bits of the 2 variables >>>>> ends up being compiled as >>>>> >>>>> %reg16384<def> = LDWi <fi#-2>, 0; mem:LD4[FixedStack-2] I32Regs:%reg16384 >>>>> %reg16385<def> = LDWi <fi#-1>, 0; mem:LD4[FixedStack-1] I32Regs:%reg16385 >>>>> %reg16386<def> = COPY %reg16384; I32Regs:%reg16386,16384 >>>>> %r...

...st3: Frame Objects: fi#-2: size=4, align=4, fixed, at location [SP+8] fi#-1: size=4, align=8, fixed, at location [SP+4] Function Live Outs: %EAX BB#0: derived from LLVM BB %entry %reg16385<def> = MOV32rm <fi#-2>, 1, %reg0, 0, %reg0; mem:LD4[FixedStack-2] GR32:%reg16385 %reg16384<def> = MOV32rm <fi#-1>, 1, %reg0, 0, %reg0; mem:LD4[FixedStack-1] GR32:%reg16384 %reg16388<def> = MOV32ri 1; GR32:%reg16388 %reg16392<def> = XOR32ri %reg16385, 4294967294, %EFLAGS<imp-def>; GR32:%reg16392,16385 %reg16391<def> = AND32rr *%reg1...

...t i16 %crc to i32 >>>> %2 = xor i32 %1, %0 >>>> %3 = and i32 %2, 1 >>>> %4 = icmp eq i32 %3, 0 >>>> >>>> which compares the lowest bits of the 2 variables >>>> ends up being compiled as >>>> >>>> %reg16384<def> = LDWi <fi#-2>, 0; mem:LD4[FixedStack-2] I32Regs:%reg16384 >>>> %reg16385<def> = LDWi <fi#-1>, 0; mem:LD4[FixedStack-1] I32Regs:%reg16385 >>>> %reg16386<def> = COPY %reg16384; I32Regs:%reg16386,16384 >>>> %reg1639...

...registers of same reg *never* overlap. Therefore, vector loads are lowered to scalar loads followed by a chain of INSERT_VECTOR_ELTs. Then we select those to INSERT_SUBREG, everything fine to that point. Status before live analisys is (non-related instrs removed): 36 %reg16388<def> = LDWr %reg16384, 0; mem:LD4[<unknown>] 68 %reg16392<def> = INSERT_SUBREG %reg16392<undef>, %reg16388<kill>, 1 76 %reg16394<def> = LDWr %reg16386<kill>, 0; mem:LD4[<unknown>] 116 %reg16400<def> = MOVEV %reg16392<kill> 124 %reg16400<def> = INSERT_SUBREG %re...

...>> %2 = xor i32 %1, %0 >>>>> %3 = and i32 %2, 1 >>>>> %4 = icmp eq i32 %3, 0 >>>>> >>>>> which compares the lowest bits of the 2 variables >>>>> ends up being compiled as >>>>> >>>>> %reg16384<def> = LDWi <fi#-2>, 0; mem:LD4[FixedStack-2] I32Regs:%reg16384 >>>>> %reg16385<def> = LDWi <fi#-1>, 0; mem:LD4[FixedStack-1] I32Regs:%reg16385 >>>>> %reg16386<def> = COPY %reg16384; I32Regs:%reg16386,16384 >>>>>...

...s gives me this code before instr sel: # Machine code for function foo: Function Live Ins: %R25R24 in reg%16384, %R23R22 in reg%16385 Function Live Outs: %R25R24 BB#0: derived from LLVM BB %entry Live Ins: %R25R24 %R23R22 %reg16385<def> = COPY %R23R22; WDREGS:%reg16385 // COPY B %reg16384<def> = COPY %R25R24; WDREGS:%reg16384 // COPY A %reg16387<def> = COPY %reg16384:ssub_0; GPR8:%reg16387 WDREGS:%reg16384 // EXTRACT LO BYTE OF A %reg16388<def> = COPY %reg16385:ssub_0; GPR8:%reg16388 WDREGS:%reg16385 // EXTRACT LO BYTE OF B %reg16389<def> = COPY...

...gt;, 1, %reg0, 0, %reg0; mem:LD2[FixedStack-2] GR32:%reg16390 > %reg16385<def> = COPY %reg16390:sub_16bit<kill>; GR16:%reg16385 GR32:%reg16390 > %reg16391<def> = MOVZX32rm16 <fi#-1>, 1, %reg0, 0, %reg0; mem:LD2[FixedStack-1] GR32:%reg16391 > %reg16384<def> = COPY %reg16391:sub_16bit<kill>; GR16:%reg16384 GR32:%reg16391 > Successors according to CFG: BB#1 MachineOperands can refer to sub-registers of virtual registers. That is what is happening here. It is not specific to COPY instructions, but it happens a lot for them. You...

...before register allocation: MOV32mi <fi#2>, 1, %reg0, 0, %reg0, 3; mem:ST4[%a] MOV32mi <fi#3>, 1, %reg0, 0, %reg0, 5; mem:ST4[%b] MOV32mi <fi#5>, 1, %reg0, 0, %reg0, 4; mem:ST4[%d] MOV32mi <fi#6>, 1, %reg0, 0, %reg0, 100; mem:ST4[%x] %reg16384<def> = MOV32rm <fi#3>, 1, %reg0, 0, %reg0; mem:LD4[%b] GR32:%reg16384 CMP32mr <fi#2>, 1, %reg0, 0, %reg0, %reg16384<kill>, %EFLAGS<imp-def>; mem:LD4[%a] GR32:%reg16384 JLE_4 <BB#2>, %EFLAGS<imp-use,kill> The machine code after register all...

...>>>>>> %3 = and i32 %2, 1 >>>>>> %4 = icmp eq i32 %3, 0 >>>>>> >>>>>> which compares the lowest bits of the 2 variables >>>>>> ends up being compiled as >>>>>> >>>>>> %reg16384<def> = LDWi <fi#-2>, 0; mem:LD4[FixedStack-2] I32Regs:%reg16384 >>>>>> %reg16385<def> = LDWi <fi#-1>, 0; mem:LD4[FixedStack-1] I32Regs:%reg16385 >>>>>> %reg16386<def> = COPY %reg16384; I32Regs:%reg16386,16384 >>>>...

There are a lot of load/store instructions for accessing variable in stack slot. The following message is use "llc -march=ppc32" command and dump from MachineFunction. %reg16384<def> = LWZ 0, <fi#6>; mem:LD4[%b] GPRC:%reg16384 %reg16385<def> = LWZ 0, <fi#5>; mem:LD4[%c] GPRC:%reg16385 %reg16386<def> = ADD4 %reg16384<kill>, %reg16385<kill>; GPRC:%reg16386,16384,16385 STW %reg16386<kill>, 0, <fi#7>...

On Jul 28, 2010, at 12:25 PM, Carlos Sánchez de La Lama wrote: > Which after register coalescing gets transformed into: > > 36 %reg16404:1<def> = LDWr %reg16384, 0; mem:LD4[<unknown>] > 76 %reg16394<def> = LDWr %reg16386<kill>, 0; mem:LD4[<unknown>] > 124 %reg16404<def> = INSERT_SUBREG %reg16404, %reg16394<kill>, 2 > 132 %reg16401<def> = LDWr %reg16390<kill>, 0; mem:LD4[<unknown>] > 172 %reg...

...70f200: ch = br_cc 0x170f000, 0x170ed00, 0x170dc60, 0x170ec00, 0x170ef00 [ID=19] 0x170f000: ch = TokenFactor 0x170e560, 0x170e760, 0x170e960 [ID=18] 0x170e560: ch = CopyToReg 0x16d5748, 0x170e460, 0x170df60 [ID=15] 0x16d5748: ch = EntryToken [ORD=1] [ID=0] 0x170e460: i16 = Register %reg16384 [ID=5] 0x170df60: i16,ch = CopyFromReg 0x16d5748, 0x170de60 [ID=12] 0x16d5748: ch = EntryToken [ORD=1] [ID=0] 0x170de60: i16 = Register %reg16388 [ID=2] 0x170e760: ch = CopyToReg 0x16d5748, 0x170e660, 0x170e160 [ID=16] 0x16d5748: ch = EntryToken [ORD=1] [ID=0] 0x1...

...; <i64> [#uses=1] %xor2 = xor i64 %xor, %b ; <i64> [#uses=1] ret i64 %xor2 } produces these instructions before coalescing: 4L %reg16387<def> = COPY %R3<kill> 12L %reg16386<def> = COPY %R2<kill> 28L %reg16384<def> = COPY %R0<kill> 36L %reg16388<def> = COPY %reg16385<kill> 44L %reg16388<def>, %CPSR<def,dead> = tEOR %reg16388, %reg16387<kill>, pred:14, pred:%reg0 56L %reg16389<def> = COPY %reg16384<kill> 64L %reg16389<def>, %CPSR&...

On Sat, Sep 4, 2010 at 1:31 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > > On Sep 4, 2010, at 11:21 AM, Borja Ferrer wrote: > >> I've noticed this pattern happening with other operators aswell, but used xor in this example. As i said before, i tried with different register allocation orders, but it will produce always the same result. GCC is emitting longer