search for: reg16

...t;> Selecting: t3: ch,glue = CopyToReg t0, Register:i16 %R5, >>>> Constant:i16<127> >>>> >>>> In the instruction selection phase, what pattern would that match? I've >>>> constructed this so far: >>>> >>>> (??? REG16:$dst, i16imm:$src) >>>> >>>> but the problem is, I can't determine what to use as ???. There is an >>>> ISD::CopyToReg enum value, but I don't know how that translates to the >>>> string to use in the pattern. >>>> >>>>...

So there's a DAG that looks like this in the debug output: Selecting: t3: ch,glue = CopyToReg t0, Register:i16 %R5, Constant:i16<127> In the instruction selection phase, what pattern would that match? I've constructed this so far: (??? REG16:$dst, i16imm:$src) but the problem is, I can't determine what to use as ???. There is an ISD::CopyToReg enum value, but I don't know how that translates to the string to use in the pattern. And more generally, how do I find out from a DAG diagram like the ones output by -view-isel-dags wh...

...looks like this in the debug output: >> >> Selecting: t3: ch,glue = CopyToReg t0, Register:i16 %R5, >> Constant:i16<127> >> >> In the instruction selection phase, what pattern would that match? I've >> constructed this so far: >> >> (??? REG16:$dst, i16imm:$src) >> >> but the problem is, I can't determine what to use as ???. There is an >> ISD::CopyToReg enum value, but I don't know how that translates to the >> string to use in the pattern. >> >> And more generally, how do I find out from a DA...

...I will try this out. I hadn’t realised that TableGen was restricted to matching instructions with more than one output operand. I’m assuming that this is only a limitation for inferring an instruction from the patterns, because it does seem to manage schedules okay. Curiously, my memory Reg32+Reg16 pattern is very similar to yours (the 16-bit offset is sign-extended though): // Memory address: 32-bit base register + 16-bit offset register def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", []>; def MEMrr : Operand<iPTR> { let PrintMethod = "printMemOffsetO...

...t the end of the “Selection DAG Select Phase” in “The LLVM Target-Independent Code Generator”, http://llvm.org/docs/CodeGenerator.html#selectiondag-select-phase. I’ve not actually checked TableGen though so can’t be 100% sure that the documentation is still in date. Curiously, my memory Reg32+Reg16 pattern is very similar to yours (the 16-bit offset is sign-extended though): // Memory address: 32-bit base register + 16-bit offset register def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", []>; def MEMrr : Operand<iPTR> { let PrintMethod = "printMemOffsetO...

I have a rudimentary implementation for load and store instructions, where the memory address operand is automatically post-incremented when the load or store instruction is issued. However, this is currently coded using custom lowering, and explicit pattern matching in the 'ISelDAGtoDAG' implementation. But it seems to me that I ought to be able to achieve this exclusively using