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...reply your message for <https://stat.ethz.ch/pipermail/r-help/2008-April/160966.html>[R] predict.glm & newdata posted on Fri Apr 4 21:02:24 CEST 2008 You say it ##works fine but it does not: if you look at the length of yhat2, you will find 100 and not 200 as expected. In fact predict(reg1, data=x2) gives the same results as predict(reg1). So I am still looking for a solution of this problem. best regards Maurice =========== Hi, could it be the "newdata" argument? When I run predict with the newdata argument, I get an error message - a different one though. The sec...

...when compiling with and without -g (with the exception of " DBG_VALUE" instructions). The only difference I can see is the value assigned to the slot index for each instruction. As an example, without -g a snippet of a basic block looks like this: 32B %vreg29<def> = LDImm 1; REG1:%vreg29 36B %vreg44<def> = LDImm 1103515245; REG1:%vreg44 40B %vreg143:vsub32_1<def,read-undef> = LDImm 0; REG2:%vreg143 44B %vreg68<def> = LDImm 12345; REG1:%vreg68 64B %vreg143:vsub32_0<def> = COPY %vreg143:vsub32_1; REG2:%vreg143 72B %vr...

...straight-forward RISC, but it does not have hardware interlocks, i.e. data hazards involving memory access must be resolved by the compiler, either by scheduling unrelated instructions or by inserting NOOPs into the load delay slots: ---- For example, code which looks like that: load 0x1234, reg1 noop noop add reg1, 1 load 0x1236, reg2 can be safely transformed to: load 0x1234, reg1 load 0x1236, reg2 noop add reg1, 1 ---- It pleased us quite a lot when we found the HazardRecognizer-class. Without much effort we could assist LLVM to transform code like shown above (with simple (SDUse, de...

We have a test that looks like this… define void @array16_store() { ; CHECK-LABEL: array16_store: ; CHECK: ldi [[REG1:r[0-9]+]], 204 ; CHECK: ldi [[REG2:r[0-9]+]], 170 ; CHECK: sts int.array+3, [[REG2]] ; CHECK: sts int.array+2, [[REG1]] ; CHECK: ldi [[REG1:r[0-9]+]], 187 ; CHECK: ldi [[REG2:r[0-9]+]], 170 ; CHECK: sts int.array+1, [[REG2]] ; CHECK: sts int.array, [[REG1]] ; CHECK: ldi [[REG1:r[0-9]+]], 221 ; C...

Hello, I'm writing a backend for an architecture that only has LOAD Instructions that first copy the old value of the target register in another register and after that load the provided value into the register. Example of an addition: load a, reg1; // -> copies old value of reg1 in reg2 and loads value from a into reg1 load b, reg1; // -> copies old value of reg1 in reg2 and loads value from b into reg1 add reg1, reg2; // adds values from a and b and saves the result into reg1 So I need to describe the "load X, reg1" Instruc...

...gt; hardware interlocks, i.e. data hazards involving memory access must be > resolved by the compiler, either by scheduling unrelated > instructions or > by inserting NOOPs into the load delay slots: > > ---- > > For example, code which looks like that: > > load 0x1234, reg1 > noop > noop > add reg1, 1 > load 0x1236, reg2 > > can be safely transformed to: > > load 0x1234, reg1 > load 0x1236, reg2 > noop > add reg1, 1 > > ---- > > It pleased us quite a lot when we found the HazardRecognizer-class. > Without much effort we...

...iling with and without -g (with the exception of "DBG_VALUE" instructions). The only difference I can see is the value assigned to the slot index for each instruction. As an example, without -g a snippet of a basic block looks like this: > > 32B %vreg29<def> = LDImm 1; REG1:%vreg29 > 36B %vreg44<def> = LDImm 1103515245; REG1:%vreg44 > 40B %vreg143:vsub32_1<def,read-undef> = LDImm 0; REG2:%vreg143 > 44B %vreg68<def> = LDImm 12345; REG1:%vreg68 > 64B %vreg143:vsub32_0<def> = COPY %vreg143:vsub32_1; REG2:%vr...

...iling with and without -g (with the exception of "DBG_VALUE" instructions). The only difference I can see is the value assigned to the slot index for each instruction. As an example, without -g a snippet of a basic block looks like this: > > 32B %vreg29<def> = LDImm 1; REG1:%vreg29 > 36B %vreg44<def> = LDImm 1103515245; REG1:%vreg44 > 40B %vreg143:vsub32_1<def,read-undef> = LDImm 0; REG2:%vreg143 > 44B %vreg68<def> = LDImm 12345; REG1:%vreg68 > 64B %vreg143:vsub32_0<def> = COPY %vreg143:vsub32_1; REG2:%vr...

Hi folks, I'm running into this weird issue where the register spills appear to be missing for an "if" block for some reason. For example, the original if/else blocks: --- if reg0 // storeRegToStackSlot for reg1 // do something - missing a load for reg1? else // storeRegToStackSlot for reg1 // do something // loadRegFromStackSlot for reg1 end ---- I tried looking in the LLVM spiller code but it looked like the load should have already been generated at that point. Any suggestions on what I should look fo...

Each of the data sets contains monthly observations on price indices for 7 countries. I use the fitted values from reg1 in the reg2 model. The interior loop executes without error as long as I explicitly specify the data set, i.e. data=dat70. However the code fails to execute if I specify the model in the form of the commented line, i. e reg1 <-dynlm(form1,data=Dnames[j]) I get the following error message: Er...

Hi,   A question on something which normally should be easy !   I perform a linear regression using lm function:   > reg1 <- lm (a b+c+d, data = database1)   Then I try to perform the Chow (1960) test (structural change test) on my regression. I know the breakpoint date. I try the following code like it is described in the “Examples” section of the “strucchange” package :   > sctest(reg1, data = database1, type...

...Saba Department of Economics Auburn University Email: sabaric at auburn.edu Phone: 334 844-2922 anscombe<-read.table(fname, header=TRUE) names(anscombe)<-c("x1","y1","x2","y2","x3","y3","x4","y4") reg1<-lm(y1~1 + x1, data=anscombe) reg2<-lm(y2~1 + x2, data=anscombe) reg3<-lm(y3~1 + x3, data=anscombe) reg4<-lm(y4~1 + x4, data=anscombe) summary(reg1) summary(reg2) summary(reg3) summary(reg4) par(mfrow=c(2,2)) plot(x1,y1) abline(reg1) plot(x2,y2) abline(reg2) plot(x3,y3) abline(re...

...: # sample data: id<-rep(1:20) n<-c(10,20,13,22,28,12,12,36,19,12,36,75,33,121,37,14,40,16,14,20) r<-c(.68,.56,.23,.64,.49,-.04,.49,.33,.58,.18,-.11,.27,.26,.40,.49, .51,.40,.34,.42,.16) mod2<-factor(c(rep(c(1,2,3,4),5))) da<-data.frame(id, n, r, mod1, mod2) reg0<-lm(da$r ~ 1) reg1<-lm(da$r ~ da$mod1) reg2<-lm(da$r ~ da$mod1 + da$mod2) # This is as far as I get with the function: MRfit <- function( ...) { models <- list(...) fit<- anova(models) return(fit) } MRfit(reg0,reg1,reg2) # This is what I get from R: # Error in UseMethod("anova") : #...

> Of course, and the point is that, for example, on x86_64, the zext here is free. I'm still trying to understand the problem... > > In the example you provided in your previous e-mail, we choose the solution: > > `GEP @Global, zext(V)` -> `GEP (@Global + zext VStart), {i64 0,+,1}` > `V` -> `trunc({i64 0,+,1}) + VStart` > > instead of the actually-better

...; wrote: > > On Fri, Mar 8, 2019 at 1:45 AM Carl Peto via llvm-dev > <llvm-dev at lists.llvm.org> wrote: >> >> We have a test that looks like this… >> >> define void @array16_store() { >> ; CHECK-LABEL: array16_store: >> >> ; CHECK: ldi [[REG1:r[0-9]+]], 204 >> ; CHECK: ldi [[REG2:r[0-9]+]], 170 >> ; CHECK: sts int.array+3, [[REG2]] >> ; CHECK: sts int.array+2, [[REG1]] >> >> ; CHECK: ldi [[REG1:r[0-9]+]], 187 >> ; CHECK: ldi [[REG2:r[0-9]+]], 170 >> ; CHECK: sts int.array+1, [[REG2]] >> ;...

Hi all - I'm stumped by the following mdl <- glm(resp ~ . , data = df, family=binomial, offset = ofst) WORKS yhat <- predict(mdl) WORKS yhat <- predict(mdl,newdata = df) FAILS Error in drop(X[, piv, drop = FALSE] %*% beta[piv]) : subscript out of bounds I've tried without offset, quoting binomial. The offset variable ofst IS in df. Previous postings indicate possible

Hi Evan, thanks for your response. On Mon, 19 Jan 2009, Evan Cheng wrote: >> For example, code which looks like that: >> >> load 0x1234, reg1 >> noop >> noop >> add reg1, 1 >> load 0x1236, reg2 >> >> can be safely transformed to: >> >> load 0x1234, reg1 >> load 0x1236, reg2 >> noop >> add reg1, 1 >> > The register allocator doesn't reschedule code. It can coa...

...re expanded to library calls aren't maintaining the proper ordering in relation to other chains in the DAG. The following snippet of a DAG demonstrates the problem. t0: ch = EntryToken t2: i64,ch,glue = CopyFromReg t0, Register:i64 %reg0 t4: i64,ch,glue = CopyFromReg t2:1, Register:i64 %reg1, t2:1 t6: i64,ch,glue = CopyFromReg t4:1, Register:i64 %reg2, t4:1 t8: i64,ch,glue = CopyFromReg t6:1, Register:i64 %reg3, t6:1 t11: ch = CopyToReg t0, Register:i64 %vreg0, t2 t13: ch = CopyToReg t0, Register:i64 %vreg1, t4 t15: ch = CopyToReg t0, Register:i64 %vreg2, t8...

...ght that systemfit was for situations when there are more than one structural equation in the model. Anyway I probed with the two ways and I obtained similar results. Below, I show the program lines: *Program lines 1:* * * *>#### First option: applying tsls ####* *>library (sem)* *>Reg1 <-tsls (LnP~Sc+Ag+Ag2+Var+R+D,~I2+Ag+Ag2+Var+R+D) * *>summary (Reg1)* * * *>#### Second option: applying systemfit ####* *>library (systemfit)* *>RS <- LnP~Sc+Ag+Ag2+Var+R+D # structural equation* *>Inst <- ~I2+Ag+Ag2+Var+R+D # instrumental variables* *>label...

Hello~   Did any one have used the package 'orcutt' ?   I find that it can not work smoothly in a single variable regression. I use the example following, it function very well.   But when I regress "cons" on "price" (use the "reg1<-lm(cons~price+income+temp)") , then  use "reg11<-cochrane.orcutt(reg1) ". There is an error message “Error in X[, -1] %*% regCO$coeff[-1] : non-conformable arguments”.   Is this a bug for this function?   > price<-c(  0.27,  0.28,  0.28,  0.28,  0.27,  0.26,  0.28  ,0.27...