Displaying 3 results from an estimated 3 matches for "reg1069".
Did you mean:
reg1029
2008 Apr 01
1
[LLVMdev] IMPLICIT_DEF
Can someone explain where things like IMPLICIT_DEF_FR64 come from?
I believe something is noticing a use before def and inserting some kind of
bogus code to compensate. The machine instructions look like this (x86):
%reg1069<def> = IMPLICIT_DEF_FR64
FsMOVLPDmr %reg0, 1, %reg0, 0, %reg1069
This is no good -- it stores to zero.
Thanks.
-Dave
2007 Jul 12
1
[LLVMdev] backend problem with LiveInterval::removeRange
...60
SU(1): 0x88ca7d8: i32 = ADDiu 0x88cb218, 0x88ca840
SU(2): 0x88c9dd8: ch = SW 0x88ca7d8, 0x88c9d70, 0x88c9d08, 0x88cb218:1
Selected machine code:
cond_next46: 0x88c8430, LLVM BB @0x88bee00, ID#13:
Predecessors according to CFG: 0x88c8140 (#8) 0x88c83a0 (#12)
%reg1068 = LW 0, <fi#6>
%reg1069 = ADDiu %reg1068, 1
SW %reg1069, 0, <fi#6>
Successors according to CFG: 0x88c84c0 (#14)
Total amount of phi nodes to update: 0
Replacing.3 0x88cac40: i1 = setcc 0x88caa50, 0x88caab8, 0x88cabd8
With: 0x88cae20: i1 = setcc 0x88c9dd8, 0x88cadb8, 0x88cabd8
Replacing.3 0x88cae20: i1 = setcc...
2004 Jun 22
3
[LLVMdev] Linearscan allocator bug?
...eg1060
%reg1061 = - %ar7, 4
%reg1062 = move 0
store %reg1061, %reg1062
%reg1063 = - %ar7, 5
store %reg1063, %reg1064
%reg1065 = - %ar7, 6
%reg1066 = move 0
store %reg1065, %reg1066
%reg1067 = - %ar7, 7
%reg1068 = move 1
store %reg1067, %reg1068
call <ga:printf>
%ar7 = - %ar7, 8
%reg1069 = move %gr7
return
# End machine code for testBooleanNot().
Code after register allocation
# Machine code for testBooleanNot():
<fi #-4> is 4 bytes fixed at location [SP-80]
<fi #-3> is 4 bytes fixed at location [SP-76]
<fi #-2> is 4 bytes fixed at location [SP-72]
<...