Displaying 6 results from an estimated 6 matches for "reg1065".
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reg1025
2008 Oct 02
0
[LLVMdev] Making Sense of ISel DAG Output
...0x391c8b0: v2f64 = scalar_to_vector 0x391ac10 srcLineNum= 10
0x3927b10: <multiple use>
0x3923100: v2f64 = vector_shuffle 0x391c970, 0x391c8b0, 0x3927b10<0,2>
srcLineNum= 10
The code that gets produced looks like this:
%reg1071<def> = MOVSD2PDrm %reg1026, 8, %reg1065, 4294967288, Mem:LD(8,8)
[r66428 + 0]LD(8,8) [r78427 + 0] ; srcLine 10
%reg1072<def> = MOVSD2PDrm %reg1026, 8, %reg1065, 4294967288, Mem:LD(8,8)
[r66428 + 0]LD(8,8) [r78427 + 0] ; srcLine 10
%reg1073<def> = SHUFPDrri %reg1071, %reg1072, 0 ; srcLine 10
Note that %reg1026 and %reg...
2008 Oct 02
6
[LLVMdev] Making Sense of ISel DAG Output
...ctor 0x391ac10 srcLineNum= 10
> 0x3927b10: <multiple use>
> 0x3923100: v2f64 = vector_shuffle 0x391c970, 0x391c8b0,
> 0x3927b10<0,2> srcLineNum= 10
>
> The code that gets produced looks like this:
>
> %reg1071<def> = MOVSD2PDrm %reg1026, 8, %reg1065, 4294967288, Mem:LD(8,8)
> [r66428 + 0]LD(8,8) [r78427 + 0] ; srcLine 10
> %reg1072<def> = MOVSD2PDrm %reg1026, 8, %reg1065, 4294967288, Mem:LD(8,8)
> [r66428 + 0]LD(8,8) [r78427 + 0] ; srcLine 10
> %reg1073<def> = SHUFPDrri %reg1071, %reg1072, 0 ; srcLine 10
Actrually...
2008 Oct 02
4
[LLVMdev] Making Sense of ISel DAG Output
I'm debugging some X86 patterns and I want to understand the debug dumps from
isel better.
Here's some example output:
0x391bc40: i64,ch = load 0x3922c50, 0x391b8d0, 0x38dc530 <0x39053e0:0> <sext
i32> alignment=4 srcLineNum= 10
0x3922c50: <multiple use>
0x391bc40: <multiple use>
0x3856ab0: <multiple use>
0x3914520: i64 =
2008 Oct 03
0
[LLVMdev] Making Sense of ISel DAG Output
...10
>> 0x3927b10: <multiple use>
>> 0x3923100: v2f64 = vector_shuffle 0x391c970, 0x391c8b0,
>> 0x3927b10<0,2> srcLineNum= 10
>>
>> The code that gets produced looks like this:
>>
>> %reg1071<def> = MOVSD2PDrm %reg1026, 8, %reg1065, 4294967288,
>> Mem:LD(8,8)
>> [r66428 + 0]LD(8,8) [r78427 + 0] ; srcLine 10
>> %reg1072<def> = MOVSD2PDrm %reg1026, 8, %reg1065, 4294967288,
>> Mem:LD(8,8)
>> [r66428 + 0]LD(8,8) [r78427 + 0] ; srcLine 10
>> %reg1073<def> = SHUFPDrri %reg1071...
2007 Jul 12
1
[LLVMdev] backend problem with LiveInterval::removeRange
...32 = SLT 0x88c9b38, 0x88ca7d8
SU(3): 0x88c9540: ch = BNE 0x88c9d08, 0x88c9e28, 0x88ca850, 0x88c9b38:1
Selected machine code:
bb38: 0x88c8310, LLVM BB @0x88bed50, ID#11:
Predecessors according to CFG: 0x88c8218 (#9) 0x88c8280 (#10)
%reg1063 = ADDiu %ZERO, 8193
%reg1064 = LW 0, <fi#7>
%reg1065 = SLT %reg1064, %reg1063
BNE %reg1065, %ZERO, mbb<bb32,0x88c8280>
Successors according to CFG: 0x88c8280 (#10) 0x88c83a0 (#12)
Total amount of phi nodes to update: 0
Lowered selection DAG:
SelectionDAG has 7 nodes:
0x88c8940: i32 = FrameIndex <8>
0x88c9970: i32 = undef
0x8...
2004 Jun 22
3
[LLVMdev] Linearscan allocator bug?
...1055 = move %reg1056
%ar7 = + %ar7, 8
%reg1057 = - %ar7, 1
store %reg1057, %reg1055
%reg1058 = - %ar7, 2
store %reg1058, %reg1029
%reg1059 = - %ar7, 3
store %reg1059, %reg1060
%reg1061 = - %ar7, 4
%reg1062 = move 0
store %reg1061, %reg1062
%reg1063 = - %ar7, 5
store %reg1063, %reg1064
%reg1065 = - %ar7, 6
%reg1066 = move 0
store %reg1065, %reg1066
%reg1067 = - %ar7, 7
%reg1068 = move 1
store %reg1067, %reg1068
call <ga:printf>
%ar7 = - %ar7, 8
%reg1069 = move %gr7
return
# End machine code for testBooleanNot().
Code after register allocation
# Machine code for testBoolea...