Displaying 6 results from an estimated 6 matches for "reg1064".
Did you mean:
reg1024
2008 Oct 02
6
[LLVMdev] Making Sense of ISel DAG Output
...g1033, 1, %reg0, 0, Mem:LD(4,4) [iv.161162 +
0] ; srcLine 10
%reg1062<def> = MOVSDrm %reg1026, 8, %reg1061, 4294967288, Mem:LD(8,8)
[r30158 + 0] ; srcLine 10
%reg1063<def> = MOVSD2PDrm %reg1026, 8, %reg1059, 4294967288, Mem:LD(8,8)
[r30158 + 0]LD(8,8) [r45154 + 0] ; srcLine 10
%reg1064<def> = MOVSD2PDrm %reg1026, 8, %reg1059, 4294967288, Mem:LD(8,8)
[r30158 + 0]LD(8,8) [r45154 + 0] ; srcLine 10
%reg1065<def> = SHUFPDrri %reg1063, %reg1064, 0 ; srcLine 10
Where the <bleep> are these extra dead MOVSDrms coming from? Note that the
extra MOVSDrms at least see...
2008 Oct 03
0
[LLVMdev] Making Sense of ISel DAG Output
...2 +
> 0] ; srcLine 10
> %reg1062<def> = MOVSDrm %reg1026, 8, %reg1061, 4294967288,
> Mem:LD(8,8)
> [r30158 + 0] ; srcLine 10
> %reg1063<def> = MOVSD2PDrm %reg1026, 8, %reg1059, 4294967288,
> Mem:LD(8,8)
> [r30158 + 0]LD(8,8) [r45154 + 0] ; srcLine 10
> %reg1064<def> = MOVSD2PDrm %reg1026, 8, %reg1059, 4294967288,
> Mem:LD(8,8)
> [r30158 + 0]LD(8,8) [r45154 + 0] ; srcLine 10
> %reg1065<def> = SHUFPDrri %reg1063, %reg1064, 0 ; srcLine 10
>
> Where the <bleep> are these extra dead MOVSDrms coming from? Note
> that...
2008 Oct 02
0
[LLVMdev] Making Sense of ISel DAG Output
On Thursday 02 October 2008 11:37, David Greene wrote:
> I'll try ot write a small example and send it in a bit.
Ok, here's what I'm trying to do:
let AddedComplexity = 40 in {
def : Pat<(v2f64 (vector_shuffle (v2f64 (scalar_to_vector (loadf64 addr:
$src1))),
(v2f64 (scalar_to_vector (loadf64 addr:
$src2))),
2008 Oct 02
4
[LLVMdev] Making Sense of ISel DAG Output
I'm debugging some X86 patterns and I want to understand the debug dumps from
isel better.
Here's some example output:
0x391bc40: i64,ch = load 0x3922c50, 0x391b8d0, 0x38dc530 <0x39053e0:0> <sext
i32> alignment=4 srcLineNum= 10
0x3922c50: <multiple use>
0x391bc40: <multiple use>
0x3856ab0: <multiple use>
0x3914520: i64 =
2007 Jul 12
1
[LLVMdev] backend problem with LiveInterval::removeRange
..., 0x88c9060
SU(2): 0x88c9d08: i32 = SLT 0x88c9b38, 0x88ca7d8
SU(3): 0x88c9540: ch = BNE 0x88c9d08, 0x88c9e28, 0x88ca850, 0x88c9b38:1
Selected machine code:
bb38: 0x88c8310, LLVM BB @0x88bed50, ID#11:
Predecessors according to CFG: 0x88c8218 (#9) 0x88c8280 (#10)
%reg1063 = ADDiu %ZERO, 8193
%reg1064 = LW 0, <fi#7>
%reg1065 = SLT %reg1064, %reg1063
BNE %reg1065, %ZERO, mbb<bb32,0x88c8280>
Successors according to CFG: 0x88c8280 (#10) 0x88c83a0 (#12)
Total amount of phi nodes to update: 0
Lowered selection DAG:
SelectionDAG has 7 nodes:
0x88c8940: i32 = FrameIndex <8>...
2004 Jun 22
3
[LLVMdev] Linearscan allocator bug?
...g1052 = move 0
store %reg1051, %reg1052
%reg1053 = - %ar7, 7
store %reg1053, %reg1039
call <ga:printf>
%ar7 = - %ar7, 8
%reg1054 = move %gr7
return
shortcirc_done.1 (0x8065d90, LLVM BB @0x8060320):
%reg1060 = phi %reg1032, mbb<shortcirc_next.0.selectcont.selectcont,0x8065c10>
%reg1064 = phi %reg1035, mbb<shortcirc_next.0.selectcont.selectcont,0x8065c10>
%reg1056 = move <ga:.str_1>
%reg1055 = move %reg1056
%ar7 = + %ar7, 8
%reg1057 = - %ar7, 1
store %reg1057, %reg1055
%reg1058 = - %ar7, 2
store %reg1058, %reg1029
%reg1059 = - %ar7, 3
store %reg1059, %reg1060...