Displaying 10 results from an estimated 10 matches for "reg1060".
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2010 Jun 15
4
[LLVMdev] Simpler subreg ops in machine code IR
...%reg1045<def> = EXTRACT_SUBREG %reg1044<kill>, 4
%reg1045<def> = COPY %reg1044:sub_32bit<kill>
%reg1045<def> = INSERT_SUBREG %reg1045, %reg1044<kill>, 4
%reg1045:sub_32bit<def> = COPY %reg1044<kill>
%reg1050:ssub_0<def> = EXTRACT_SUBREG %reg1060:dsub_1<kill>, ssub_0
%reg1050:ssub_0<def> = COPY %reg1060:ssub_2<kill>
It will also replace the TargetInstrInfo::copyRegToReg hook when copying virtual registers:
%reg1050 = COPY %reg1044<kill>
It will be lowered with a TII.copyRegToReg() call in LowerSubregsInstruction...
2010 Jun 16
0
[LLVMdev] Simpler subreg ops in machine code IR
...T_SUBREG %reg1044<kill>, 4
> %reg1045<def> = COPY %reg1044:sub_32bit<kill>
>
> %reg1045<def> = INSERT_SUBREG %reg1045, %reg1044<kill>, 4
> %reg1045:sub_32bit<def> = COPY %reg1044<kill>
>
> %reg1050:ssub_0<def> = EXTRACT_SUBREG %reg1060:dsub_1<kill>, ssub_0
> %reg1050:ssub_0<def> = COPY %reg1060:ssub_2<kill>
>
> It will also replace the TargetInstrInfo::copyRegToReg hook when copying virtual registers:
>
> %reg1050 = COPY %reg1044<kill>
>
> It will be lowered with a TII.copyRegToRe...
2008 Oct 02
6
[LLVMdev] Making Sense of ISel DAG Output
...Actrually, it's worse than this. I wanted to check to make sure something
else wasn't causing the problem but it appears to come from isel. The full
output for the DAG looks like this:
%reg1059<def> = MOVSX64rm32 %reg1033, 1, %reg0, 4, Mem:LD(4,4) [tmp163 +
0] ; srcLine 10
%reg1060<def> = MOVSDrm %reg1026, 8, %reg1059, 4294967288, Mem:LD(8,8)
[r45154 + 0] ; srcLine 10
%reg1061<def> = MOVSX64rm32 %reg1033, 1, %reg0, 0, Mem:LD(4,4) [iv.161162 +
0] ; srcLine 10
%reg1062<def> = MOVSDrm %reg1026, 8, %reg1061, 4294967288, Mem:LD(8,8)
[r30158 + 0] ; srcLine...
2004 Jun 22
3
[LLVMdev] Linearscan allocator bug?
...nly predecessor of this basic block is jump on line
90. The problem is that gr6 is not initialized in the interval from the
function entry till the jump.
I also attach the debug dumps from my backend.
The basic block in question is shortcirc_done.1 (line 198 in the log). It
starts with:
%reg1060 = phi %reg1032, mbb<shortcirc_next.0.selectcont.selectcont,
The predecessor is at line 155 and the register 1032 is assigned a value on
line 140 (in shortcirc_next.0.selectcont):
%reg1032 = move %reg103
After register allocation the code in shortcirc_done.1 is (line 334):
%gr2 = mo...
2007 Jul 12
1
[LLVMdev] backend problem with LiveInterval::removeRange
...0x88ca6a8, 0x88ca940
Selected machine code:
bb32: 0x88c8280, LLVM BB @0x88becf8, ID#10:
%reg1055 = LUi <ga:flags.2176>
%reg1056 = LW 0, <fi#7>
%reg1057 = ADDiu %reg1055, <ga:flags.2176>
%reg1058 = ADDiu %ZERO, 0
%reg1059 = ADDu %reg1057, %reg1056
SB %reg1058, 0, %reg1059
%reg1060 = LW 0, <fi#7>
%reg1061 = LW 0, <fi#6>
%reg1062 = ADDu %reg1060, %reg1061
SW %reg1062, 0, <fi#7>
Successors according to CFG: 0x88c8310 (#11)
Total amount of phi nodes to update: 0
Replacing.3 0x88ca7d8: i1 = setcc 0x88c9bb0, 0x88c9d08, 0x88c9e28
With: 0x88cb218: i1 = setc...
2008 Oct 03
0
[LLVMdev] Making Sense of ISel DAG Output
...d to check to make sure
> something
> else wasn't causing the problem but it appears to come from isel.
> The full
> output for the DAG looks like this:
>
> %reg1059<def> = MOVSX64rm32 %reg1033, 1, %reg0, 4, Mem:LD(4,4)
> [tmp163 +
> 0] ; srcLine 10
> %reg1060<def> = MOVSDrm %reg1026, 8, %reg1059, 4294967288,
> Mem:LD(8,8)
> [r45154 + 0] ; srcLine 10
> %reg1061<def> = MOVSX64rm32 %reg1033, 1, %reg0, 0, Mem:LD(4,4) [iv.
> 161162 +
> 0] ; srcLine 10
> %reg1062<def> = MOVSDrm %reg1026, 8, %reg1061, 4294967288,
&g...
2008 Oct 02
0
[LLVMdev] Making Sense of ISel DAG Output
On Thursday 02 October 2008 11:37, David Greene wrote:
> I'll try ot write a small example and send it in a bit.
Ok, here's what I'm trying to do:
let AddedComplexity = 40 in {
def : Pat<(v2f64 (vector_shuffle (v2f64 (scalar_to_vector (loadf64 addr:
$src1))),
(v2f64 (scalar_to_vector (loadf64 addr:
$src2))),
2004 Jun 22
0
[LLVMdev] Linearscan allocator bug?
...uction (implement isMoveInstr), so instructinos
like 'gr1 = gr1' will go away and you'll get coallescing. :)
-Chris
> I also attach the debug dumps from my backend.
>
> The basic block in question is shortcirc_done.1 (line 198 in the log). It
> starts with:
>
> %reg1060 = phi %reg1032, mbb<shortcirc_next.0.selectcont.selectcont,
>
> The predecessor is at line 155 and the register 1032 is assigned a value on
> line 140 (in shortcirc_next.0.selectcont):
>
> %reg1032 = move %reg103
>
> After register allocation the code in shortcirc_done.1...
2008 Oct 02
4
[LLVMdev] Making Sense of ISel DAG Output
I'm debugging some X86 patterns and I want to understand the debug dumps from
isel better.
Here's some example output:
0x391bc40: i64,ch = load 0x3922c50, 0x391b8d0, 0x38dc530 <0x39053e0:0> <sext
i32> alignment=4 srcLineNum= 10
0x3922c50: <multiple use>
0x391bc40: <multiple use>
0x3856ab0: <multiple use>
0x3914520: i64 =
2010 Sep 07
3
[LLVMdev] MachineMemOperand and dependence information
...g1030, %reg0, 4100, pred:14, pred:%reg0;
mem:LD4[%uglygep10]
(after transformation)
%reg1043<def> = LDR %reg1040, %reg0, 4100, pred:14, pred:%reg0;
mem:LD4[%uglygep10]
...
%reg1053<def> = LDR %reg1050, %reg0, 4100, pred:14, pred:%reg0;
mem:LD4[%uglygep10]
...
%reg1063<def> = LDR %reg1060, %reg0, 4100, pred:14, pred:%reg0;
mem:LD4[%uglygep10]
In this example, should mem:LD4[%uglygep10] be removed from the three
instructions so that passes run later will not use dependence information
that is no longer correct?
Thank you.
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