Displaying 6 results from an estimated 6 matches for "reg1059".
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reg1029
2008 Oct 02
6
[LLVMdev] Making Sense of ISel DAG Output
...78427 + 0] ; srcLine 10
> %reg1073<def> = SHUFPDrri %reg1071, %reg1072, 0 ; srcLine 10
Actrually, it's worse than this. I wanted to check to make sure something
else wasn't causing the problem but it appears to come from isel. The full
output for the DAG looks like this:
%reg1059<def> = MOVSX64rm32 %reg1033, 1, %reg0, 4, Mem:LD(4,4) [tmp163 +
0] ; srcLine 10
%reg1060<def> = MOVSDrm %reg1026, 8, %reg1059, 4294967288, Mem:LD(8,8)
[r45154 + 0] ; srcLine 10
%reg1061<def> = MOVSX64rm32 %reg1033, 1, %reg0, 0, Mem:LD(4,4) [iv.161162 +
0] ; srcLine 10
%re...
2008 Oct 03
0
[LLVMdev] Making Sense of ISel DAG Output
...lt;def> = SHUFPDrri %reg1071, %reg1072, 0 ; srcLine 10
>
> Actrually, it's worse than this. I wanted to check to make sure
> something
> else wasn't causing the problem but it appears to come from isel.
> The full
> output for the DAG looks like this:
>
> %reg1059<def> = MOVSX64rm32 %reg1033, 1, %reg0, 4, Mem:LD(4,4)
> [tmp163 +
> 0] ; srcLine 10
> %reg1060<def> = MOVSDrm %reg1026, 8, %reg1059, 4294967288,
> Mem:LD(8,8)
> [r45154 + 0] ; srcLine 10
> %reg1061<def> = MOVSX64rm32 %reg1033, 1, %reg0, 0, Mem:LD(4,4) [iv...
2008 Oct 02
0
[LLVMdev] Making Sense of ISel DAG Output
On Thursday 02 October 2008 11:37, David Greene wrote:
> I'll try ot write a small example and send it in a bit.
Ok, here's what I'm trying to do:
let AddedComplexity = 40 in {
def : Pat<(v2f64 (vector_shuffle (v2f64 (scalar_to_vector (loadf64 addr:
$src1))),
(v2f64 (scalar_to_vector (loadf64 addr:
$src2))),
2008 Oct 02
4
[LLVMdev] Making Sense of ISel DAG Output
I'm debugging some X86 patterns and I want to understand the debug dumps from
isel better.
Here's some example output:
0x391bc40: i64,ch = load 0x3922c50, 0x391b8d0, 0x38dc530 <0x39053e0:0> <sext
i32> alignment=4 srcLineNum= 10
0x3922c50: <multiple use>
0x391bc40: <multiple use>
0x3856ab0: <multiple use>
0x3914520: i64 =
2007 Jul 12
1
[LLVMdev] backend problem with LiveInterval::removeRange
...d8, 0x88c9d60
SU(7): 0x88c9d08: ch = SW 0x88ca8d8, 0x88c9540, 0x88ca6a8, 0x88ca940
Selected machine code:
bb32: 0x88c8280, LLVM BB @0x88becf8, ID#10:
%reg1055 = LUi <ga:flags.2176>
%reg1056 = LW 0, <fi#7>
%reg1057 = ADDiu %reg1055, <ga:flags.2176>
%reg1058 = ADDiu %ZERO, 0
%reg1059 = ADDu %reg1057, %reg1056
SB %reg1058, 0, %reg1059
%reg1060 = LW 0, <fi#7>
%reg1061 = LW 0, <fi#6>
%reg1062 = ADDu %reg1060, %reg1061
SW %reg1062, 0, <fi#7>
Successors according to CFG: 0x88c8310 (#11)
Total amount of phi nodes to update: 0
Replacing.3 0x88ca7d8: i1 = se...
2004 Jun 22
3
[LLVMdev] Linearscan allocator bug?
....selectcont.selectcont,0x8065c10>
%reg1064 = phi %reg1035, mbb<shortcirc_next.0.selectcont.selectcont,0x8065c10>
%reg1056 = move <ga:.str_1>
%reg1055 = move %reg1056
%ar7 = + %ar7, 8
%reg1057 = - %ar7, 1
store %reg1057, %reg1055
%reg1058 = - %ar7, 2
store %reg1058, %reg1029
%reg1059 = - %ar7, 3
store %reg1059, %reg1060
%reg1061 = - %ar7, 4
%reg1062 = move 0
store %reg1061, %reg1062
%reg1063 = - %ar7, 5
store %reg1063, %reg1064
%reg1065 = - %ar7, 6
%reg1066 = move 0
store %reg1065, %reg1066
%reg1067 = - %ar7, 7
%reg1068 = move 1
store %reg1067, %reg1068
call <ga...