Displaying 5 results from an estimated 5 matches for "reg1057".
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2010 Apr 15
0
[LLVMdev] Question About Cloning Machine Basic Block
On Wed, 2010-04-14 at 17:30 -0700, Hisham Chowdhury wrote:
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> - Is there a utility to clone a MachineBasicBlock in LLVM
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There is CloneBasicBlock routine
in ./lib/Transforms/Utils/CloneFunction.cpp
- Sanjiv
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu
2010 Apr 15
1
[LLVMdev] Question About Cloning Machine Basic Block
Hello,
I am trying to clone a machine basic block when I ran into some issues, where I am not able to make some headway. Any of yours help is highly appreciated here:
My question is about Machine Basic Block Duplication:
- Is there a utility to clone a MachineBasicBlock in LLVM? I found utility to clone machineInstrs, but couldn’t find similar utility for MachineBasicBlock. So, I
2007 Oct 06
2
[LLVMdev] Spill Interval Generation Question
...live interval end is 257 while
%reg1330's interval start is 258. The merging code expects them to
be equal in this case where the source register is dead after the copy.
If we look at another copy where the source is dead but was NOT
spilled, we see something different:
Examining copy 420%reg1057 = MOV64rr %reg1297<kill>
MOV64rr %reg1057<d> %reg1297
Ok from regalloc
Real regs %reg1057 = %reg1297
Intervals:
%reg1057,0 = [422,1034:0) 0 at 422-(1034)
%reg1297,0 = [402,420:0)[420,422:1)[1074,1096:2) 0 at 402-(421) 1@?-(422)
2 at 1074-(1095)
Notice how the end of the second valu...
2007 Jul 12
1
[LLVMdev] backend problem with LiveInterval::removeRange
...h = TokenFactor 0x88ca7d8:1, 0x88c9d60:1
SU(2): 0x88ca8d8: i32 = ADDu 0x88ca7d8, 0x88c9d60
SU(7): 0x88c9d08: ch = SW 0x88ca8d8, 0x88c9540, 0x88ca6a8, 0x88ca940
Selected machine code:
bb32: 0x88c8280, LLVM BB @0x88becf8, ID#10:
%reg1055 = LUi <ga:flags.2176>
%reg1056 = LW 0, <fi#7>
%reg1057 = ADDiu %reg1055, <ga:flags.2176>
%reg1058 = ADDiu %ZERO, 0
%reg1059 = ADDu %reg1057, %reg1056
SB %reg1058, 0, %reg1059
%reg1060 = LW 0, <fi#7>
%reg1061 = LW 0, <fi#6>
%reg1062 = ADDu %reg1060, %reg1061
SW %reg1062, 0, <fi#7>
Successors according to CFG: 0x88c8310...
2004 Jun 22
3
[LLVMdev] Linearscan allocator bug?
...rtcirc_done.1 (0x8065d90, LLVM BB @0x8060320):
%reg1060 = phi %reg1032, mbb<shortcirc_next.0.selectcont.selectcont,0x8065c10>
%reg1064 = phi %reg1035, mbb<shortcirc_next.0.selectcont.selectcont,0x8065c10>
%reg1056 = move <ga:.str_1>
%reg1055 = move %reg1056
%ar7 = + %ar7, 8
%reg1057 = - %ar7, 1
store %reg1057, %reg1055
%reg1058 = - %ar7, 2
store %reg1058, %reg1029
%reg1059 = - %ar7, 3
store %reg1059, %reg1060
%reg1061 = - %ar7, 4
%reg1062 = move 0
store %reg1061, %reg1062
%reg1063 = - %ar7, 5
store %reg1063, %reg1064
%reg1065 = - %ar7, 6
%reg1066 = move 0
store %r...