Displaying 8 results from an estimated 8 matches for "reg1054".
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2010 Sep 07
3
[LLVMdev] MachineMemOperand and dependence information
...ineMemOperands and dependence
information.
Q1) I noticed that MachineMemOperands are lost when two LDRs are combined
and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps.
(before optimization)
%reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0;
mem:LD4[%uglygep10]
%reg1054<def> = LDR %reg1030, %reg0, 4104, pred:14, pred:%reg0;
mem:LD4[%uglygep2021]
(after optimization)
%reg1054<def>, %reg1033<def> = LDRD %reg1030, %reg0, 264, pred:14,
pred:%reg0
Are there any reasons they need to be removed?
Would it break something if both MachineMemOperands were...
2010 Sep 07
0
[LLVMdev] MachineMemOperand and dependence information
...information.
>
> Q1) I noticed that MachineMemOperands are lost when two LDRs are combined and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps.
>
> (before optimization)
> %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0; mem:LD4[%uglygep10]
> %reg1054<def> = LDR %reg1030, %reg0, 4104, pred:14, pred:%reg0; mem:LD4[%uglygep2021]
>
> (after optimization)
> %reg1054<def>, %reg1033<def> = LDRD %reg1030, %reg0, 264, pred:14, pred:%reg0
>
> Are there any reasons they need to be removed?
> Would it break something i...
2010 Sep 07
1
[LLVMdev] MachineMemOperand and dependence information
...noticed that MachineMemOperands are lost when two LDRs are combined
> and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps.
> >
> > (before optimization)
> > %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0;
> mem:LD4[%uglygep10]
> > %reg1054<def> = LDR %reg1030, %reg0, 4104, pred:14, pred:%reg0;
> mem:LD4[%uglygep2021]
> >
> > (after optimization)
> > %reg1054<def>, %reg1033<def> = LDRD %reg1030, %reg0, 264, pred:14,
> pred:%reg0
> >
> > Are there any reasons they need to be removed...
2008 Jan 16
4
[LLVMdev] LiveInterval Questions
...valid, would be the same as a.start. But this is apparently not
always the case. For example:
Predecessors according to CFG: 0x839d130 (#3) 0x8462780 (#35)
308 %reg1051 = MOV64rr %reg1227<kill>
312 %reg1052 = MOV64rr %reg1228<kill>
316 %reg1053 = MOV64rr %reg1229<kill>
320 %reg1054 = MOV64rr %reg1230<kill>
324 %reg1055<dead> = LEA64r %reg1047, 1, %reg1053, 0
328 %reg1135 = MOVSX64rr32 %reg1025
332 %reg1136 = MOV64rr %reg1135<kill>
336 %reg1136 = ADD64ri32 %reg1136, -4, %EFLAGS<imp-def,dead>
340 TEST64rr %reg1136<kill>, %reg1136, %EFLAGS<imp-de...
2008 Jan 17
0
[LLVMdev] LiveInterval Questions
...t. But this is apparently not
> always the case. For example:
>
> Predecessors according to CFG: 0x839d130 (#3) 0x8462780 (#35)
> 308 %reg1051 = MOV64rr %reg1227<kill>
> 312 %reg1052 = MOV64rr %reg1228<kill>
> 316 %reg1053 = MOV64rr %reg1229<kill>
> 320 %reg1054 = MOV64rr %reg1230<kill>
> 324 %reg1055<dead> = LEA64r %reg1047, 1, %reg1053, 0
> 328 %reg1135 = MOVSX64rr32 %reg1025
> 332 %reg1136 = MOV64rr %reg1135<kill>
> 336 %reg1136 = ADD64ri32 %reg1136, -4, %EFLAGS<imp-def,dead>
> 340 TEST64rr %reg1136<kill>, %r...
2007 Jul 12
1
[LLVMdev] backend problem with LiveInterval::removeRange
...DDu 0x88c9c08, 0x88c9c08
SU(3): 0x88c8d68: ch = SW 0x88c9640, 0x88c9ba0, 0x88c89a8, 0x88c9c08:1
SU(2): 0x88c9b38: ch = J 0x88c8940, 0x88c8d68
Selected machine code:
cond_true28: 0x88c8218, LLVM BB @0x88beca0, ID#9:
Predecessors according to CFG: 0x88c8140 (#8)
%reg1053 = LW 0, <fi#6>
%reg1054 = ADDu %reg1053, %reg1053
SW %reg1054, 0, <fi#7>
J mbb<bb38,0x88c8310>
Successors according to CFG: 0x88c8310 (#11)
Total amount of phi nodes to update: 0
Replacing.3 0x88c89a8: i32 = shl 0x88c8d28, 0x88c8940
With: 0x88c8d28: i32,ch = load 0x88c9060, 0x88c9640, 0x88c9970
Lowered...
2008 Jan 17
0
[LLVMdev] LiveInterval Questions
...rt. But this is apparently not
> always the case. For example:
>
> Predecessors according to CFG: 0x839d130 (#3) 0x8462780 (#35)
> 308 %reg1051 = MOV64rr %reg1227<kill>
> 312 %reg1052 = MOV64rr %reg1228<kill>
> 316 %reg1053 = MOV64rr %reg1229<kill>
> 320 %reg1054 = MOV64rr %reg1230<kill>
> 324 %reg1055<dead> = LEA64r %reg1047, 1, %reg1053, 0
> 328 %reg1135 = MOVSX64rr32 %reg1025
> 332 %reg1136 = MOV64rr %reg1135<kill>
> 336 %reg1136 = ADD64ri32 %reg1136, -4, %EFLAGS<imp-def,dead>
> 340 TEST64rr %reg1136<kill>, %r...
2004 Jun 22
3
[LLVMdev] Linearscan allocator bug?
...store %reg1045, %reg1046
%reg1047 = - %ar7, 4
%reg1048 = move 0
store %reg1047, %reg1048
%reg1049 = - %ar7, 5
store %reg1049, %reg1050
%reg1051 = - %ar7, 6
%reg1052 = move 0
store %reg1051, %reg1052
%reg1053 = - %ar7, 7
store %reg1053, %reg1039
call <ga:printf>
%ar7 = - %ar7, 8
%reg1054 = move %gr7
return
shortcirc_done.1 (0x8065d90, LLVM BB @0x8060320):
%reg1060 = phi %reg1032, mbb<shortcirc_next.0.selectcont.selectcont,0x8065c10>
%reg1064 = phi %reg1035, mbb<shortcirc_next.0.selectcont.selectcont,0x8065c10>
%reg1056 = move <ga:.str_1>
%reg1055 = move %reg...