Displaying 5 results from an estimated 5 matches for "reg1043".
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2010 Jun 17
0
[LLVMdev] Loopinfo Analysis
Hi Hisham,
Most likely the basic blocks are the headers of two different loops. Try running viewCFG() on the function in question to see if this is the case.
Tom
----- Original Message -----
From: "Hisham Chowdhury" <hisham_chow at yahoo.com>
To: llvmdev at cs.uiuc.edu
Sent: Wednesday, June 16, 2010 7:22:00 PM GMT -05:00 US/Canada Eastern
Subject: [LLVMdev] Loopinfo Analysis
2010 Jun 16
2
[LLVMdev] Loopinfo Analysis
Hello,
I have a question regrading the analysis pass that generates loop info from an .ll code. My previous understanding was there will be just one loop header(in the loop info) for a particular loop. But, when i use isLoopHeader() member function from the loop info class I get 'true' return value for two different basic blocks. Note both basic blocks are loop conditional block(break
2007 Jul 12
1
[LLVMdev] backend problem with LiveInterval::removeRange
...i32,ch = LW 0x88c8a20, 0x88ca290, 0x88c8bf0
SU(2): 0x88c8900: i32 = SLT 0x88c8c88, 0x88c96a8
SU(3): 0x88c99a8: ch = BNE 0x88c8900, 0x88c9640, 0x88c9540, 0x88c8c88:1
Selected machine code:
bb14: 0x88c8020, LLVM BB @0x88beb98, ID#6:
Predecessors according to CFG: 0x88c7ed8 (#4) 0x88c7f90 (#5)
%reg1043 = ADDiu %ZERO, 8193
%reg1044 = LW 0, <fi#6>
%reg1045 = SLT %reg1044, %reg1043
BNE %reg1045, %ZERO, mbb<bb9,0x88c7f90>
Successors according to CFG: 0x88c7f90 (#5) 0x88c80b0 (#7)
Total amount of phi nodes to update: 0
Lowered selection DAG:
SelectionDAG has 7 nodes:
0x88c8bf0...
2010 Sep 07
3
[LLVMdev] MachineMemOperand and dependence information
...something similar to loop unrolling and replicates and reorders
existing instructions.
For example, a single load instruction could be replicated three times.
(before transformation)
%reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0;
mem:LD4[%uglygep10]
(after transformation)
%reg1043<def> = LDR %reg1040, %reg0, 4100, pred:14, pred:%reg0;
mem:LD4[%uglygep10]
...
%reg1053<def> = LDR %reg1050, %reg0, 4100, pred:14, pred:%reg0;
mem:LD4[%uglygep10]
...
%reg1063<def> = LDR %reg1060, %reg0, 4100, pred:14, pred:%reg0;
mem:LD4[%uglygep10]
In this example, should mem:L...
2004 Jun 22
3
[LLVMdev] Linearscan allocator bug?
...move 1
shortcirc_next.1.selectcont (0x8065d30, LLVM BB @0x8063f08):
%reg1040 = phi %reg1076, mbb<shortcirc_next.1.selecttrue,0x8065cd0>, %reg1077, mbb<shortcirc_next.1,0x8065c70>
%reg1039 = move %reg1040
%reg1042 = move <ga:.str_1>
%reg1041 = move %reg1042
%ar7 = + %ar7, 8
%reg1043 = - %ar7, 1
store %reg1043, %reg1041
%reg1044 = - %ar7, 2
store %reg1044, %reg1029
%reg1045 = - %ar7, 3
store %reg1045, %reg1046
%reg1047 = - %ar7, 4
%reg1048 = move 0
store %reg1047, %reg1048
%reg1049 = - %ar7, 5
store %reg1049, %reg1050
%reg1051 = - %ar7, 6
%reg1052 = move 0
store %r...