search for: reg1040

...3<kill>, pred:14, pred:%reg0, opt:%reg0 %reg1036<def> = MOVi 0, pred:14, pred:%reg0, opt:%reg0 %reg1038<def> = MOVr %reg1024<kill>, pred:14, pred:%reg0, opt:%reg0 %reg1039<def> = MOVr %reg1025<kill>, pred:14, pred:%reg0, opt:%reg0 %reg1040<def> = MOVr %reg1036<kill>, pred:14, pred:%reg0, opt:%reg0 Successors according to CFG: BB#3 BB#3: derived from LLVM BB %bb Predecessors according to CFG: BB#2 BB#3 %reg1026<def> = MOVr %reg1038<kill>, pred:14, pred:%reg0, opt:%reg0 %reg1027<def&g...

Hi Hisham, Most likely the basic blocks are the headers of two different loops. Try running viewCFG() on the function in question to see if this is the case. Tom ----- Original Message ----- From: "Hisham Chowdhury" <hisham_chow at yahoo.com> To: llvmdev at cs.uiuc.edu Sent: Wednesday, June 16, 2010 7:22:00 PM GMT -05:00 US/Canada Eastern Subject: [LLVMdev] Loopinfo Analysis

Hello, I have a question regrading the analysis pass that generates loop info from an .ll code. My previous understanding was there will be just one loop header(in the loop info) for a particular loop. But, when i use isLoopHeader() member function from the loop info class I get 'true' return value for two different basic blocks. Note both basic blocks are loop conditional block(break

...00, 0x88c9598 SU(6): 0x88c9540: ch = SW 0x88c8a00, 0x88c8cf0, 0x88c8c88, 0x88c9600:1 Selected machine code: bb9: 0x88c7f90, LLVM BB @0x88bf3b8, ID#5: %reg1036 = LUi <ga:flags.2176> %reg1037 = LW 0, <fi#6> %reg1038 = ADDiu %reg1036, <ga:flags.2176> %reg1039 = ADDiu %ZERO, 1 %reg1040 = ADDu %reg1038, %reg1037 SB %reg1039, 0, %reg1040 %reg1041 = LW 0, <fi#6> %reg1042 = ADDiu %reg1041, 1 SW %reg1042, 0, <fi#6> Successors according to CFG: 0x88c8020 (#6) Total amount of phi nodes to update: 0 Replacing.3 0x88c8a20: i1 = setcc 0x88c8d68, 0x88c8900, 0x88ca290 Wi...

...unrolling and replicates and reorders existing instructions. For example, a single load instruction could be replicated three times. (before transformation) %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0; mem:LD4[%uglygep10] (after transformation) %reg1043<def> = LDR %reg1040, %reg0, 4100, pred:14, pred:%reg0; mem:LD4[%uglygep10] ... %reg1053<def> = LDR %reg1050, %reg0, 4100, pred:14, pred:%reg0; mem:LD4[%uglygep10] ... %reg1063<def> = LDR %reg1060, %reg0, 4100, pred:14, pred:%reg0; mem:LD4[%uglygep10] In this example, should mem:LD4[%uglygep10] be removed...

...move 1 setcc %reg1027, %reg1038 if v< goto %disp(label shortcirc_next.1.selecttrue) %reg1077 = move 0 goto %disp(label shortcirc_next.1.selectcont) shortcirc_next.1.selecttrue (0x8065cd0, LLVM BB @0x8063fb0): %reg1076 = move 1 shortcirc_next.1.selectcont (0x8065d30, LLVM BB @0x8063f08): %reg1040 = phi %reg1076, mbb<shortcirc_next.1.selecttrue,0x8065cd0>, %reg1077, mbb<shortcirc_next.1,0x8065c70> %reg1039 = move %reg1040 %reg1042 = move <ga:.str_1> %reg1041 = move %reg1042 %ar7 = + %ar7, 8 %reg1043 = - %ar7, 1 store %reg1043, %reg1041 %reg1044 = - %ar7, 2 store %re...