Displaying 5 results from an estimated 5 matches for "reg1038".
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reg1028
2010 Aug 11
1
[LLVMdev] Need advice on writing scheduling pass
..._edge
Predecessors according to CFG: BB#0
%reg1025<def> = MOVr %reg1034<kill>, pred:14, pred:%reg0, opt:%reg0
%reg1024<def> = MOVr %reg1033<kill>, pred:14, pred:%reg0, opt:%reg0
%reg1036<def> = MOVi 0, pred:14, pred:%reg0, opt:%reg0
%reg1038<def> = MOVr %reg1024<kill>, pred:14, pred:%reg0, opt:%reg0
%reg1039<def> = MOVr %reg1025<kill>, pred:14, pred:%reg0, opt:%reg0
%reg1040<def> = MOVr %reg1036<kill>, pred:14, pred:%reg0, opt:%reg0
Successors according to CFG: BB#3
BB#3: derived...
2007 Jul 12
1
[LLVMdev] backend problem with LiveInterval::removeRange
...ch = LW 0x88c8cf0, 0x88c8c88, 0x88c8900
SU(3): 0x88c8a00: i32 = ADDiu 0x88c9600, 0x88c9598
SU(6): 0x88c9540: ch = SW 0x88c8a00, 0x88c8cf0, 0x88c8c88, 0x88c9600:1
Selected machine code:
bb9: 0x88c7f90, LLVM BB @0x88bf3b8, ID#5:
%reg1036 = LUi <ga:flags.2176>
%reg1037 = LW 0, <fi#6>
%reg1038 = ADDiu %reg1036, <ga:flags.2176>
%reg1039 = ADDiu %ZERO, 1
%reg1040 = ADDu %reg1038, %reg1037
SB %reg1039, 0, %reg1040
%reg1041 = LW 0, <fi#6>
%reg1042 = ADDiu %reg1041, 1
SW %reg1042, 0, <fi#6>
Successors according to CFG: 0x88c8020 (#6)
Total amount of phi nodes to up...
2010 Jun 17
0
[LLVMdev] Loopinfo Analysis
Hi Hisham,
Most likely the basic blocks are the headers of two different loops. Try running viewCFG() on the function in question to see if this is the case.
Tom
----- Original Message -----
From: "Hisham Chowdhury" <hisham_chow at yahoo.com>
To: llvmdev at cs.uiuc.edu
Sent: Wednesday, June 16, 2010 7:22:00 PM GMT -05:00 US/Canada Eastern
Subject: [LLVMdev] Loopinfo Analysis
2010 Jun 16
2
[LLVMdev] Loopinfo Analysis
Hello,
I have a question regrading the analysis pass that generates loop info from an .ll code. My previous understanding was there will be just one loop header(in the loop info) for a particular loop. But, when i use isLoopHeader() member function from the loop info class I get 'true' return value for two different basic blocks. Note both basic blocks are loop conditional block(break
2004 Jun 22
3
[LLVMdev] Linearscan allocator bug?
...t;0 goto %disp(label shortcirc_done.1)
goto %disp(label shortcirc_next.1)
shortcirc_next.1 (0x8065c70, LLVM BB @0x8060278):
%reg1046 = phi %reg1032, mbb<shortcirc_next.0.selectcont.selectcont,0x8065c10>
%reg1050 = phi %reg1035, mbb<shortcirc_next.0.selectcont.selectcont,0x8065c10>
%reg1038 = move 1
setcc %reg1027, %reg1038
if v< goto %disp(label shortcirc_next.1.selecttrue)
%reg1077 = move 0
goto %disp(label shortcirc_next.1.selectcont)
shortcirc_next.1.selecttrue (0x8065cd0, LLVM BB @0x8063fb0):
%reg1076 = move 1
shortcirc_next.1.selectcont (0x8065d30, LLVM BB @0x8063f08):...