Displaying 7 results from an estimated 7 matches for "reg1034".
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reg1024
2006 Jun 30
3
[LLVMdev] Removing dead code
..., %reg1026
ADJCALLSTACKDOWN 56
%reg1030 = IMPLICIT_DEF_GPR
%reg1031 = LA %reg1027, <ga:.str_1>
%r3 = OR4 %reg1031, %reg1031
BL <ga:printf>, %r3
%reg1032 = OR4 %r3, %r3 <-------------------
%reg1033 = EXTSB %reg1029
%reg1034 = LA %reg1028, <ga:.str_2>
ADJCALLSTACKUP 56
ADJCALLSTACKDOWN 56
%r3 = OR4 %reg1034, %reg1034
%r4 = OR4 %reg1033, %reg1033
BL <ga:printf>, %r3, %r4
%reg1035 = OR4 %r3, %r3
ADJCALLSTACKUP 56
%r3 = OR4 %reg1030, %reg1030...
2006 Jun 30
0
[LLVMdev] Removing dead code
On Thu, 29 Jun 2006, Fernando Magno Quintao Pereira wrote:
> I am working in a register allocator for LLVM, and I realized that,
> after I perform register allocation, there is many move instructions that
> are dead code, and can safely be removed. It is easy for the RA algorithm
> to remove these instructions. It seems to me that the only instructions
> with dead definitions
2010 Sep 01
1
[LLVMdev] equivalent IR, different asm
On Sep 1, 2010, at 11:14 AM, Dale Johannesen wrote:
>
> On Sep 1, 2010, at 6:25 AMPDT, Argyrios Kyrtzidis wrote:
>
>> The attached .ll files seem equivalent, but the resulting asm from
>> 'opt-fail.ll' causes a crash to webkit.
>> I suspect the usage of registers is wrong, can someone take a look ?
>
> Yes, the code here is wrong:
>
>> movl
2006 Jun 30
2
[LLVMdev] Removing dead code
Dear guys,
I am working in a register allocator for LLVM, and I realized that,
after I perform register allocation, there is many move instructions that
are dead code, and can safely be removed. It is easy for the RA algorithm
to remove these instructions. It seems to me that the only instructions
with dead definitions that I should not remove are the calls. Is it true?
I would like to know
2007 Jul 12
1
[LLVMdev] backend problem with LiveInterval::removeRange
...5): 0x88c89c0: ch = SW 0x88c8f30, 0x88c8da0, 0x88c8958, 0x88ca1e8
SU(2): 0x88ca240: i32 = ADDiu 0x88ca2a8, 0x88c9298
SU(4): 0x88c8900: ch = SW 0x88ca240, 0x88c8da0, 0x88c8c88, 0x88c89c0
SU(3): 0x88c8d38: ch = J 0x88c9330, 0x88c8900
Selected machine code:
bb: 0x88c7ed8, LLVM BB @0x88bf360, ID#4:
%reg1034 = ADDiu %ZERO, 0
SW %reg1034, 0, <fi#8>
%reg1035 = ADDiu %ZERO, 2
SW %reg1035, 0, <fi#6>
J mbb<bb14,0x88c8020>
Successors according to CFG: 0x88c8020 (#6)
Total amount of phi nodes to update: 0
Replacing.3 0x88ca250: i32 = shl 0x88ca3e0, 0x88ca1e8
With: 0x88ca3e0: i32,ch...
2010 Aug 11
1
[LLVMdev] Need advice on writing scheduling pass
...ollows (note that information in
LiveVariables is not updated, so there may exist inconsistencies):
BB2: preheader, BB3: header & latch, BB4: exit
(before transformation)
BB#2: derived from LLVM BB %entry.bb_crit_edge
Predecessors according to CFG: BB#0
%reg1025<def> = MOVr %reg1034<kill>, pred:14, pred:%reg0, opt:%reg0
%reg1024<def> = MOVr %reg1033<kill>, pred:14, pred:%reg0, opt:%reg0
%reg1036<def> = MOVi 0, pred:14, pred:%reg0, opt:%reg0
%reg1038<def> = MOVr %reg1024<kill>, pred:14, pred:%reg0, opt:%reg0
%r...
2004 Jun 22
3
[LLVMdev] Linearscan allocator bug?
...ont)
shortcirc_next.0.selecttrue (0x8065af0, LLVM BB @0x8063bb0):
%reg1072 = move 1
shortcirc_next.0.selectcont (0x8065b50, LLVM BB @0x8063b08):
%reg1033 = phi %reg1072, mbb<shortcirc_next.0.selecttrue,0x8065af0>, %reg1073, mbb<shortcirc_next.0,0x8065a90>
%reg1032 = move %reg1033
%reg1034 = move 1
setcc %reg1025, %reg1034
if v< goto %disp(label shortcirc_next.0.selectcont.selecttrue)
%reg1075 = move 0
goto %disp(label shortcirc_next.0.selectcont.selectcont)
shortcirc_next.0.selectcont.selecttrue (0x8065bb0, LLVM BB @0x8063db0):
%reg1074 = move 1
shortcirc_next.0.selectcont...