Displaying 14 results from an estimated 14 matches for "reg1032".
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2006 Jun 30
3
[LLVMdev] Removing dead code
...g1027 = LIS <ga:.str_1>
%reg1028 = LIS <ga:.str_2>
%reg1029 = LBZ 0, %reg1026
ADJCALLSTACKDOWN 56
%reg1030 = IMPLICIT_DEF_GPR
%reg1031 = LA %reg1027, <ga:.str_1>
%r3 = OR4 %reg1031, %reg1031
BL <ga:printf>, %r3
%reg1032 = OR4 %r3, %r3 <-------------------
%reg1033 = EXTSB %reg1029
%reg1034 = LA %reg1028, <ga:.str_2>
ADJCALLSTACKUP 56
ADJCALLSTACKDOWN 56
%r3 = OR4 %reg1034, %reg1034
%r4 = OR4 %reg1033, %reg1033
BL <ga:printf>, %r3, %r4...
2009 Jan 09
2
[LLVMdev] implicit CC register Defs cause "physreg was not killed in defining block!" assert
...f().
The dump() of the MBB from the debugger looks like the following:
entry.ifcont267_crit_edge: 0x12bc368, LLVM BB @0x12bb900, ID#2:
Predecessors according to CFG: 0x12bc290 (#0) 0x12bca70 (#1)
%reg1033<def> = addC %reg1025<kill>, 0, %CCFLAGS<imp-def,dead>
%reg1032<def> = addC %reg1024<kill>, 0, %CCFLAGS<imp-def,dead>
%reg1095<def> = addC %reg1028, 0, %CCFLAGS<imp-def>
%reg1096<def> = addC %reg1029<kill>, 0, %CCFLAGS<imp-def>
%reg1097<def> = addC %reg1033<kill>, 0, %CCFLAGS<...
2009 Jan 09
0
[LLVMdev] implicit CC register Defs cause "physreg was not killed in defining block!" assert
...he MBB from the debugger looks like the following:
>
> entry.ifcont267_crit_edge: 0x12bc368, LLVM BB @0x12bb900, ID#2:
> Predecessors according to CFG: 0x12bc290 (#0) 0x12bca70 (#1)
> %reg1033<def> = addC %reg1025<kill>, 0, %CCFLAGS<imp-def,dead>
> %reg1032<def> = addC %reg1024<kill>, 0, %CCFLAGS<imp-def,dead>
> %reg1095<def> = addC %reg1028, 0, %CCFLAGS<imp-def>
> %reg1096<def> = addC %reg1029<kill>, 0, %CCFLAGS<imp-def>
> %reg1097<def> = addC %reg1033<kill>, 0,...
2010 May 09
2
[LLVMdev] Machine Verifier question.
....bc -o
Output/ReedSolomon.llc.s -verify-machineinstrs
in llvm-test/SingleSource/Benchmarks/Misc currently yields seven errors, all
of the form
*** Bad machine code: PHI operand is not live-out from predecessor ***
- function: main
- basic block: bb2.i.preheader 0x1ba7680 (BB#5)
- instruction: %reg1032<def> = PHI %reg1280, <BB#3>, %reg1287, <BB#4>
- operand 1: %reg1280
The code seems to run ok though.
Is this something that's worth looking in to, or just over zealous reporting
by the machine verifier?
Cheers,
Lang.
-------------- next part --------------
An HTML attachm...
2004 Jun 22
3
[LLVMdev] Linearscan allocator bug?
...of this basic block is jump on line
90. The problem is that gr6 is not initialized in the interval from the
function entry till the jump.
I also attach the debug dumps from my backend.
The basic block in question is shortcirc_done.1 (line 198 in the log). It
starts with:
%reg1060 = phi %reg1032, mbb<shortcirc_next.0.selectcont.selectcont,
The predecessor is at line 155 and the register 1032 is assigned a value on
line 140 (in shortcirc_next.0.selectcont):
%reg1032 = move %reg103
After register allocation the code in shortcirc_done.1 is (line 334):
%gr2 = move %gr6
the pr...
2010 May 10
0
[LLVMdev] Machine Verifier question.
...rify-machineinstrs
>
> in llvm-test/SingleSource/Benchmarks/Misc currently yields seven errors, all of the form
>
> *** Bad machine code: PHI operand is not live-out from predecessor ***
> - function: main
> - basic block: bb2.i.preheader 0x1ba7680 (BB#5)
> - instruction: %reg1032<def> = PHI %reg1280, <BB#3>, %reg1287, <BB#4>
> - operand 1: %reg1280
>
> The code seems to run ok though.
>
> Is this something that's worth looking in to, or just over zealous reporting by the machine verifier?
That sounds like a proper bug. Can you tell...
2004 Jul 06
1
[LLVMdev] Moving between registers of different classes
...egister can't be AND-ed with anything, I move the value into general purpose
register, to "and" and then move it into address register. Unfortunately, the
register allocator crashes. Here's machine code:
%reg1030 = - %reg1027, 1
%reg1031 = move %reg1030
%reg1032 = + %reg1031, -2
%reg1033 = move %reg1032
%ar1 = load64 %gr1<def>, %reg1033
and here's assertion:
llc: LiveIntervals.cpp:507: void llvm::LiveIntervals::joinIntervals():
Assertion `rcA == rcB && "registers must be of the same class"' failed.
(gdb) u...
2006 Jun 30
0
[LLVMdev] Removing dead code
On Fri, 30 Jun 2006, Fernando Magno Quintao Pereira wrote:
> where %reg1032 is dead.
Right. One of the jobs of the register allocator is to coallesce register
copies. Once coallesced, they can be removed.
> I'm removing these instructions. In Linear scan, they are removed too.
> I'm removing all the dead definitions from instructions that are not
>...
2006 Jun 30
0
[LLVMdev] Removing dead code
On Thu, 29 Jun 2006, Fernando Magno Quintao Pereira wrote:
> I am working in a register allocator for LLVM, and I realized that,
> after I perform register allocation, there is many move instructions that
> are dead code, and can safely be removed. It is easy for the RA algorithm
> to remove these instructions. It seems to me that the only instructions
> with dead definitions
2006 Jun 30
2
[LLVMdev] Removing dead code
Dear guys,
I am working in a register allocator for LLVM, and I realized that,
after I perform register allocation, there is many move instructions that
are dead code, and can safely be removed. It is easy for the RA algorithm
to remove these instructions. It seems to me that the only instructions
with dead definitions that I should not remove are the calls. Is it true?
I would like to know
2004 Jun 22
0
[LLVMdev] Linearscan allocator bug?
...nt isMoveInstr), so instructinos
like 'gr1 = gr1' will go away and you'll get coallescing. :)
-Chris
> I also attach the debug dumps from my backend.
>
> The basic block in question is shortcirc_done.1 (line 198 in the log). It
> starts with:
>
> %reg1060 = phi %reg1032, mbb<shortcirc_next.0.selectcont.selectcont,
>
> The predecessor is at line 155 and the register 1032 is assigned a value on
> line 140 (in shortcirc_next.0.selectcont):
>
> %reg1032 = move %reg103
>
> After register allocation the code in shortcirc_done.1 is (line 334):...
2009 Jan 12
1
[LLVMdev] implicit CC register Defs cause "physreg was not killed in defining block!" assert
...mbining these two passes - unless you tell
me they don't get marked dead because of an implementation flaw in my
backend (or something completely else : )
Thanks again,
Christian
>> %reg1033<def> = addC %reg1025<kill>, 0, %CCFLAGS<imp-def,dead>
>> %reg1032<def> = addC %reg1024<kill>, 0, %CCFLAGS<imp-def,dead>
>> %reg1095<def> = addC %reg1028, 0, %CCFLAGS<imp-def>
>> %reg1096<def> = addC %reg1029<kill>, 0, %CCFLAGS<imp-def>
>> %reg1097<def> = addC %reg1033<...
2007 Jul 12
1
[LLVMdev] backend problem with LiveInterval::removeRange
...0x88c8cf0, 0x88c8b58, 0x88c8968, 0x88c8cf0:1
SU(3): 0x88c9150: ch = SW 0x88c8d88, 0x88c8b58, 0x88c8a68, 0x88ca1e8
SU(2): 0x88c8af0: ch = J 0x88c8a00, 0x88c9150
Selected machine code:
cond_next: 0x88c7e48, LLVM BB @0x88be1b8, ID#3:
Predecessors according to CFG: 0x88c79a8 (#1) 0x88c7db8 (#2)
%reg1032 = ADDiu %ZERO, 0
%reg1033 = LW 0, <fi#3>
SW %reg1033, 0, <fi#5>
SW %reg1032, 0, <fi#8>
J mbb<bb55,0x88c8550>
Successors according to CFG: 0x88c8550 (#15)
Total amount of phi nodes to update: 0
Lowered selection DAG:
SelectionDAG has 10 nodes:
0x88c9060: i32 = undef...
2010 Sep 09
2
[LLVMdev] Possible missed optimization? 2.0
...nce!
68 %reg1030<def> = MOVRdRr %R1<kill>
Inspecting R1,inf = [38,39:0)[54,70:1)[94,95:2) 0 at 38-(39) 1 at 54-(70) 2 at 94-(95) and %reg1030,0.000000e+00 = [70,78:0) 0 at 70-(78):
Joined. Result = R1,inf = [38,39:1)[54,78:0)[94,95:2) 0 at 54-(78) 1 at 38-(39) 2 at 94-(95)
100 %reg1032<def> = MOVRdRr %R0<kill>
Inspecting R0,inf = [38,46:0)[54,62:1)[94,102:2) 0 at 38-(46) 1 at 54-(62) 2 at 94-(102) and %reg1032,0.000000e+00 = [102,110:0) 0 at 102-(110):
Joined. Result = R0,inf = [38,46:1)[54,62:2)[94,110:0) 0 at 94-(110) 1 at 38-(46) 2 at 54-(62)
124 %R15<d...