search for: reg02

...~Sepal.Length + Sepal.Length:Species, data=iris) summary(reg01) It gives me a summary table with lm for the first factor, i.e setosa, and the effects of each levels of Species on interactions, which mean on the slope. Now, i would like a model with intercept =0. I should write this: data(iris) reg02 <- lm(Petal.Length~Sepal.Length + Sepal.Length:Species - 1 , data=iris) summary(reg02) ...But results is meaningless for me... Any idea to fit a model like this? Thanks a lot ! Julien -- ********************************************* Julien Leblud Numerical Ecology of Aquatic Systems Mons...

...e affected systems and see if the memory areas are listed there > (and if the attributes are somehow wrong if found). >From Asus X542UQ: # cat /proc/mtrr reg00: base=0x0c0000000 ( 3072MB), size= 1024MB, count=1: uncachable reg01: base=0x0a0000000 ( 2560MB), size= 512MB, count=1: uncachable reg02: base=0x090000000 ( 2304MB), size= 256MB, count=1: uncachable reg03: base=0x08c000000 ( 2240MB), size= 64MB, count=1: uncachable reg04: base=0x08b800000 ( 2232MB), size= 8MB, count=1: uncachable # cat /sys/kernel/debug/x86/pat_memtype_list PAT memtype list: write-back @ 0x84a23000-0x84a24000...

...gt; Yes, can you check if the failing device BAR is included in any of the > above entries? If not then it is probably not related. mtrr again for reference: reg00: base=0x0c0000000 ( 3072MB), size= 1024MB, count=1: uncachable reg01: base=0x0a0000000 ( 2560MB), size= 512MB, count=1: uncachable reg02: base=0x090000000 ( 2304MB), size= 256MB, count=1: uncachable reg03: base=0x08c000000 ( 2240MB), size= 64MB, count=1: uncachable reg04: base=0x08b800000 ( 2232MB), size= 8MB, count=1: uncachable The PCI bridge is: 00:1c.0 PCI bridge: Intel Corporation Sunrise Point-LP PCI Express Root Port...

...card and IDL 7.1, everything works just fine. By the way, we have never had any such problem with all our DELL boxes using CentOS and IDL on T3400, the /proc/mtrr: reg00: base=0x00000000 ( 0MB), size=65536MB: write-back, count=1 reg01: base=0x3ff00000 (1023MB), size= 1MB: uncachable, count=1 reg02: base=0x40000000 (1024MB), size=1024MB: uncachable, count=1 reg03: base=0x80000000 (2048MB), size=2048MB: uncachable, count=1 When googling, someone out there suggest manually configure the MTRR, can somebody help us how to configure this six-core's MTRR? I am guessing this must be MTRR relate...

On Tue, Sep 04, 2018 at 09:52:02AM +0800, Daniel Drake wrote: > # cat /proc/mtrr > reg00: base=0x0c0000000 ( 3072MB), size= 1024MB, count=1: uncachable > reg01: base=0x0a0000000 ( 2560MB), size= 512MB, count=1: uncachable > reg02: base=0x090000000 ( 2304MB), size= 256MB, count=1: uncachable > reg03: base=0x08c000000 ( 2240MB), size= 64MB, count=1: uncachable > reg04: base=0x08b800000 ( 2232MB), size= 8MB, count=1: uncachable > > # cat /sys/kernel/debug/x86/pat_memtype_list > PAT memtype list: > writ...

On Sat, Sep 1, 2018 at 3:12 AM, Bjorn Helgaas <helgaas at kernel.org> wrote: > If true, this sounds like some sort of erratum, so it would be good to > get some input from Intel, and I cc'd a few Intel folks. Yes, it would be great to get their input. > It's interesting that all the systems below are from Asus. That makes > me think there's some BIOS or SMM

...M: 2039M Apr 11 17:25:36 kernel: mtrr_cleanup: can not find optimal value Apr 11 17:25:36 kernel: please specify mtrr_gran_size/mtrr_chunk_size cat /proc/mtrr reg00: base=0x0d0000000 ( 3328MB), size= 256MB, count=1: uncachable reg01: base=0x0e0000000 ( 3584MB), size= 512MB, count=1: uncachable reg02: base=0x000000000 ( 0MB), size= 8192MB, count=1: write-back reg03: base=0x200000000 ( 8192MB), size= 512MB, count=1: write-back reg04: base=0x220000000 ( 8704MB), size= 256MB, count=1: write-back reg05: base=0x0cf700000 ( 3319MB), size= 1MB, count=1: uncachable reg06: base=0x0cf800000 ( 332...