Displaying 6 results from an estimated 6 matches for "read_sysreg32".
2013 Feb 22
48
[PATCH v3 00/46] initial arm v8 (64-bit) support
This round implements all of the review comments from V2 and all patches
are now acked. Unless there are any objections I intend to apply later
this morning.
Ian.
2013 Aug 29
2
[PATCH] xen/arm: Don't set the ACTLR SMP bit for 64 bit guests
...+++++++++++++-----
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index cb0424d..00f2d14 100644
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -470,11 +470,19 @@ int vcpu_initialise(struct vcpu *v)
v->arch.actlr = READ_SYSREG32(ACTLR_EL1);
- /* XXX: Handle other than CA15 cpus */
- if ( v->domain->max_vcpus > 1 )
- v->arch.actlr |= ACTLR_CA15_SMP;
- else
- v->arch.actlr &= ~ACTLR_CA15_SMP;
+ if ( is_pv32_domain(v->domain) )
+ {
+ /*
+ * ACTLR is implement...
2013 Jan 23
132
[PATCH 00/45] initial arm v8 (64-bit) support
First off, Apologies for the massive patch series...
This series boots a 32-bit dom0 kernel to a command prompt on an ARMv8
(AArch64) model. The kernel is the same one as I am currently using with
the 32 bit hypervisor
I haven''t yet tried starting a guest or anything super advanced like
that ;-). Also there is not real support for 64-bit domains at all,
although in one or two places I
2013 Dec 03
7
[PATCH] xen: arm: Fixing ttbcr (TCR_EL1 for AArch64) size.
This patch fixes size of ttbcr register (TCR_EL1 in case of AArch64)
and it''s programming considering size in case of context switch.
Currently ttbcr is defined as 32b register but for AArch64 TCR_EL1
size is 64b.
Signed-off-by: Anup Patel <anup.patel@linaro.org>
Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
---
xen/arch/arm/domain.c | 8
2013 Oct 08
3
Re: [PATCH v4 1/9] xen/arm: Implement hvm save and restore
...the Free Software Foundation, Inc., 59 Temple
>> + * Place - Suite 330, Boston, MA 02111-1307 USA.
>> + */
>> +
>> +#include
>> +#include
>> +
>> +void arch_hvm_save(struct domain *d, struct hvm_save_header *hdr)
>> +{
>> + hdr->cpuid = READ_SYSREG32(MIDR_EL1);
>> +}
>> +
>> +int arch_hvm_load(struct domain *d, struct hvm_save_header *hdr)
>> +{
>> + uint32_t cpuid;
>> +
>> + if ( hdr->magic != HVM_FILE_MAGIC )
>> + {
>> + printk(XENLOG_G_ERR "HVM%d restore: bad magic...
2013 Aug 13
13
[PATCH v8 8/5] Add UART support and arch timer initialization for OMAP5
Since OMAP UART has a few distinct features than common 8250 UART, I
re-implemented its driver rather than porting it based on ns16550.c.
There are mainly two big differences between the implementations. First,
OMAP UART introduces the concept of register access mode, which divides
the register map into seperated space. Switching the access mode is then
necessary when configuring it. Second, THRE