search for: rc16_1

...perandInfo = (ops RC32, RC16_l); } but it is still happy to select for offset’s > 16-bits. There is something I am just not yet getting right, but it looks like I am on the right track. I believe that the MIOperandInfo will constrain the register class for your 16-bit offset operand to RC16_1 but in itself it won’t affect the matching of the operand. Your SelectADDRrr will need to contain code to match an i32 added to a sign-extended i16. If you’ve already done that, then I’m out of ideas, sorry. Steve -------------- next part -------------- An HTML attachment was scrubbed... URL:...

Thanks Steve, I will try this out. I hadn’t realised that TableGen was restricted to matching instructions with more than one output operand. I’m assuming that this is only a limitation for inferring an instruction from the patterns, because it does seem to manage schedules okay. Curiously, my memory Reg32+Reg16 pattern is very similar to yours (the 16-bit offset is sign-extended though):