Displaying 3 results from an estimated 3 matches for "rc16_l".
2015 Nov 02
2
Questions about load/store incrementing address modes
...fset is sign-extended though):
// Memory address: 32-bit base register + 16-bit offset register
def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", []>;
def MEMrr : Operand<iPTR> {
let PrintMethod = "printMemOffsetOperand";
let MIOperandInfo = (ops RC32, RC16_l);
}
but it is still happy to select for offset’s > 16-bits. There is something I am just not yet getting right, but it looks like I am on the right track.
All the best,
MartinO
From: Steve Montgomery [mailto:stephen.montgomery3 at btinternet.com]
Sent: 30 October 2...
2015 Nov 02
2
Questions about load/store incrementing address modes
...fset is sign-extended though):
// Memory address: 32-bit base register + 16-bit offset register
def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", []>;
def MEMrr : Operand<iPTR> {
let PrintMethod = "printMemOffsetOperand";
let MIOperandInfo = (ops RC32, RC16_l);
}
but it is still happy to select for offset’s > 16-bits. There is something I am just not yet getting right, but it looks like I am on the right track.
I believe that the MIOperandInfo will constrain the register class for your 16-bit offset operand to RC16_1 but in itself it won’t...
2015 Oct 30
2
Questions about load/store incrementing address modes
I have a rudimentary implementation for load and store instructions, where
the memory address operand is automatically post-incremented when the load
or store instruction is issued. However, this is currently coded using
custom lowering, and explicit pattern matching in the 'ISelDAGtoDAG'
implementation. But it seems to me that I ought to be able to achieve this
exclusively using