search for: rax

...ouble %rtb_Sum3_737, 0.000000e+00 %_rtB_739 = load %B_repro_T*, %B_repro_T** %_rtB_, align 8 br i1 %603, label %true73, label %false74 Now, in broken.asm, notice the same merge128 is missing the branch instruction: .LBB6_55: # %merge128 movq 184(%rsp), %rcx movq %rax, 728(%rcx) movq 184(%rsp), %rax movq 728(%rax), %rcx movq %rcx, 736(%rax) movq 184(%rsp), %rax movq $0, 744(%rax) movq 184(%rsp), %rax movq $0, 752(%rax) movq 184(%rsp), %rax movq $0, 760(%rax) movq 176(%rsp), %rax movsd 5608(%rax), %xmm0 # xmm0 = mem[0],zero movq 184(%rsp), %rax mulsd 648(%r...

...st -mrecip=all:0 \ -c -o vec.o vec.cc I get the following codegen: 0000000000000160 <_Z4fct6PDv4_f>: 160: 31 c0 xor %eax,%eax 162: c4 e2 79 18 05 00 00 vbroadcastss 0x0(%rip),%xmm0 # 16b <_Z4fct6PDv4_f+0xb> 169: 00 00 16b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) 170: c5 f8 59 0c 07 vmulps (%rdi,%rax,1),%xmm0,%xmm1 175: c5 f8 29 0c 07 vmovaps %xmm1,(%rdi,%rax,1) 17a: c5 f8 59 4c 07 10 vmulps 0x10(%rdi,%rax,1),%xmm0,%xmm1 180: c5 f8 29 4c 07 10 vmovaps %xmm1,0x10(%rdi,%rax,1) 186: c5 f8 59 4c 07 20 vmulps 0x20(%rdi,%rax,1)...

...d by JIT is not as good as that generated by clang or llc. Here is an example: -------------------------------------------------------------------- source fragment ==> clang or llc struct { uint64_t a[10]; } *p; mov 0x8(%rax),%rdx p->a[2] = p->a[1]; mov %rdx,0x10(%rax) p->a[3] = p->a[1]; ==> mov %rdx,0x18(%rax) p->a[4] = p->a[2]; mov %rdx,0x20(%rax) p->a[5] = p->a[4]; mov %rdx,0x28(%rax) -------------...

...une 2007 14:11, Evan Cheng wrote: > On Jun 26, 2007, at 11:20 AM, David A. Greene wrote: > > 28 %AL<dead> = MOV8rr %reg1024<kill>, %EAX<imp-def> > > MOV8rr %mreg(2)<d> %reg1024 %mreg(17)<d> > > 32 CALL64pcrel32 <ga:printf>, %RDI<kill>, %RAX<imp-def>, %RCX<imp- > > def,dead>, > > %RDX<imp-def,dead>, %RSI<imp-def,dead>, %RDI<imp-def,dead>, > > %R8<imp-def,dead>, %R9<imp-def,dead>, %R10<imp-def,dead>, %R11<imp- > > def,dead>, > > %FP0<imp-def,dead>,...

...d by JIT is not as good as that generated by clang or llc. Here is an example: -------------------------------------------------------------------- source fragment ==> clang or llc struct { uint64_t a[10]; } *p; mov 0x8(%rax),%rdx p->a[2] = p->a[1]; mov %rdx,0x10(%rax) p->a[3] = p->a[1]; ==> mov %rdx,0x18(%rax) p->a[4] = p->a[2]; mov %rdx,0x20(%rax) p->a[5] = p->a[4]; mov %rdx,0x28(%rax) -------------...

...points to 0x69382E which is the beginning of ExecEvalVar function. Then I save the object code into a file after implementing notifyObjectCompiled method. IrExprGetValue: 0x00007fe4cc6c2000: push %rbp 0x00007fe4cc6c2001: mov %rsp,%rbp 0x00007fe4cc6c2004: mov 0x10(%rdi),%rax 0x00007fe4cc6c2008: pop %rbp 0x00007fe4cc6c2009: jmpq *%rax 0x00007fe4cc6c200b: nopl 0x0(%rax,%rax,1) JittedOpExpr: 0x00007fe4cc6c2010: push %rbp 0x00007fe4cc6c2011: mov %rsp,%rbp *0x00007fe4cc6c2014: movabs $0x7fe4801fa1f8,%rax* 0x00007fe4cc6c201e: movabs $0x7fe48...

...; > > implicitly: > > > 28 %AL<dead> = MOV8rr %reg1024<kill>, %EAX<imp-def> > > > MOV8rr %mreg(2)<d> %reg1024 %mreg(17)<d> > > > > So their live ranges start at 28+2. > > Yep, this makes sense to me. But AL is a subregister of RAX too, > so shouldn't it have a live interval that starts there as well? > > 48 %EAX = MOV32rr %reg1027<kill>, %RAX<imp-use,kill>, %RAX<imp-def> > > MOV32rr %mreg(17)<d> %reg1027 %mreg(74) %mreg(74)<d> > > > > Def of sub-register use and d...

Hi the appended IR code does not optimize to my liking :) this is the interesting part in x86_64, that got produced via clang -Os: --- movq -16(%r12), %rax movl -4(%rax), %ecx andl $2298949, %ecx ## imm = 0x231445 cmpq $2298949, (%rax,%rcx) ## imm = 0x231445 leaq 8(%rax,%rcx), %rax cmovneq %r15, %rax movl $2298949, %esi ## imm = 0x231445 movq %r12, %rdi movq %r14, %rdx callq *(%rax) --- and clang -O3: --- movq -16(%r...

https://bugs.freedesktop.org/show_bug.cgi?id=98506 Bug ID: 98506 Summary: Pagefault in gf100_vm_flush Product: xorg Version: git Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: Driver/nouveau Assignee: nouveau at lists.freedesktop.org

On Jun 26, 2007, at 11:20 AM, David A. Greene wrote: > > 28 %AL<dead> = MOV8rr %reg1024<kill>, %EAX<imp-def> > MOV8rr %mreg(2)<d> %reg1024 %mreg(17)<d> > 32 CALL64pcrel32 <ga:printf>, %RDI<kill>, %RAX<imp-def>, %RCX<imp- > def,dead>, > %RDX<imp-def,dead>, %RSI<imp-def,dead>, %RDI<imp-def,dead>, > %R8<imp-def,dead>, %R9<imp-def,dead>, %R10<imp-def,dead>, %R11<imp- > def,dead>, > %FP0<imp-def,dead>, %FP1<imp-def,dead&g...

...cmp edi, 2 jnz loc_100000F29 mov rdi, [rsi+8] ; char * xor r14d, r14d xor esi, esi ; char ** mov edx, 0Ah ; int call _strtol mov r15, rax shl rax, 20h mov rsi, offset __mh_execute_header add rsi, rax sar rsi, 20h ; size_t mov edi, 4 ; size_t call _calloc lea edx, [r15-1]...

...<ga:initialized$$$CFE_id_cc092431_main> 24 %RDI = MOV64rr %reg1025<kill> MOV64rr %mreg(78)<d> %reg1025 28 %AL<dead> = MOV8rr %reg1024<kill>, %EAX<imp-def> MOV8rr %mreg(2)<d> %reg1024 %mreg(17)<d> 32 CALL64pcrel32 <ga:printf>, %RDI<kill>, %RAX<imp-def>, %RCX<imp-def,dead>, %RDX<imp-def,dead>, %RSI<imp-def,dead>, %RDI<imp-def,dead>, %R8<imp-def,dead>, %R9<imp-def,dead>, %R10<imp-def,dead>, %R11<imp-def,dead>, %FP0<imp-def,dead>, %FP1<imp-def,dead>, %FP2<imp-def,dead&g...

...0F29 >> mov rdi, [rsi+8] ; char * >> xor r14d, r14d >> xor esi, esi ; char ** >> mov edx, 0Ah ; int >> call _strtol >> mov r15, rax >> shl rax, 20h >> mov rsi, offset __mh_execute_header >> add rsi, rax >> sar rsi, 20h ; size_t >> mov edi, 4 ; size_t >> call _...

...ptimize these instructions? Thanks. %sub.ptr.sub.i6.i.i.i.i = sub <2 x i64> %sub.ptr.lhs.cast.i4.i.i.i.i, %sub.ptr.rhs.cast.i5.i.i.i.i %sub.ptr.div.i7.i.i.i.i = sdiv <2 x i64> %sub.ptr.sub.i6.i.i.i.i, <i64 24, i64 24> Assembly: vpsubq %xmm6, %xmm5, %xmm5 vmovq %xmm5, %rax movabsq $3074457345618258603, %rbx # imm = 0x2AAAAAAAAAAAAAAB imulq %rbx movq %rdx, %rcx movq %rcx, %rax shrq $63, %rax shrq $2, %rcx addl %eax, %ecx vpextrq $1, %xmm5, %rax imulq %rbx movq %rdx, %rax shrq $63, %rax shr...

...i, [rsi+8] ; char * >>>> xor r14d, r14d >>>> xor esi, esi ; char ** >>>> mov edx, 0Ah ; int >>>> call _strtol >>>> mov r15, rax >>>> shl rax, 20h >>>> mov rsi, offset __mh_execute_header >>>> add rsi, rax >>>> sar rsi, 20h ; size_t >>>> mov edi, 4 ; s...

...1, Evan Cheng wrote: >> On Jun 26, 2007, at 11:20 AM, David A. Greene wrote: >>> 28 %AL<dead> = MOV8rr %reg1024<kill>, %EAX<imp-def> >>> MOV8rr %mreg(2)<d> %reg1024 %mreg(17)<d> >>> 32 CALL64pcrel32 <ga:printf>, %RDI<kill>, %RAX<imp-def>, %RCX<imp- >>> def,dead>, >>> %RDX<imp-def,dead>, %RSI<imp-def,dead>, %RDI<imp-def,dead>, >>> %R8<imp-def,dead>, %R9<imp-def,dead>, %R10<imp-def,dead>, %R11<imp- >>> def,dead>, >>> %FP0<im...

...S b/arch/x86/power/hibernate_asm_64.S > index ce8da3a0412c..6fdd7bbc3c33 100644 > --- a/arch/x86/power/hibernate_asm_64.S > +++ b/arch/x86/power/hibernate_asm_64.S > @@ -24,7 +24,7 @@ > #include <asm/frame.h> > > ENTRY(swsusp_arch_suspend) > - movq $saved_context, %rax > + leaq saved_context(%rip), %rax > movq %rsp, pt_regs_sp(%rax) > movq %rbp, pt_regs_bp(%rax) > movq %rsi, pt_regs_si(%rax) > @@ -115,7 +115,7 @@ ENTRY(restore_registers) > movq %rax, %cr4; # turn PGE back on > > /* We don't restore %rax, it must be 0 anywa...

...S b/arch/x86/power/hibernate_asm_64.S > index ce8da3a0412c..6fdd7bbc3c33 100644 > --- a/arch/x86/power/hibernate_asm_64.S > +++ b/arch/x86/power/hibernate_asm_64.S > @@ -24,7 +24,7 @@ > #include <asm/frame.h> > > ENTRY(swsusp_arch_suspend) > - movq $saved_context, %rax > + leaq saved_context(%rip), %rax > movq %rsp, pt_regs_sp(%rax) > movq %rbp, pt_regs_bp(%rax) > movq %rsi, pt_regs_si(%rax) > @@ -115,7 +115,7 @@ ENTRY(restore_registers) > movq %rax, %cr4; # turn PGE back on > > /* We don't restore %rax, it must be 0 anywa...

...sub.i6.i.i.i.i = sub <2 x i64> %sub.ptr.lhs.cast.i4.i.i.i.i, %sub.ptr.rhs.cast.i5.i.i.i.i >> %sub.ptr.div.i7.i.i.i.i = sdiv <2 x i64> %sub.ptr.sub.i6.i.i.i.i, <i64 24, i64 24> >> >> Assembly: >> vpsubq %xmm6, %xmm5, %xmm5 >> vmovq %xmm5, %rax >> movabsq $3074457345618258603, %rbx # imm = 0x2AAAAAAAAAAAAAAB >> imulq %rbx >> movq %rdx, %rcx >> movq %rcx, %rax >> shrq $63, %rax >> shrq $2, %rcx >> addl %eax, %ecx >> vpextrq $1, %xmm5, %...

...-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: > > Hi > > the appended IR code does not optimize to my liking :) > > this is the interesting part in x86_64, that got produced via clang -Os: > --- > movq -16(%r12), %rax > movl -4(%rax), %ecx > andl $2298949, %ecx ## imm = 0x231445 > cmpq $2298949, (%rax,%rcx) ## imm = 0x231445 > leaq 8(%rax,%rcx), %rax > cmovneq %r15, %rax > movl $2298949, %esi...