search for: ramfc

- In the current situation the padding that is added is dangerous to write to, userspace could potentially overwrite parts of another bo. - Depth and stencil buffers are supposed to be large enough in general so the waste of memory should be acceptable. - Alternatives are hiding the padding from users or splitting vram into 2 zones. Signed-off-by: Maarten Maathuis <madman2003 at gmail.com>

...struct nouveau_fifo_engine fifo; - spinlock_t lock; }; struct nouveau_pll_vals { @@ -534,6 +533,9 @@ struct drm_nouveau_private { struct nouveau_engine engine; struct nouveau_channel *channel; + /* For PFIFO and PGRAPH. */ + spinlock_t context_switch_lock; + /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ struct nouveau_gpuobj *ramht; uint32_t ramin_rsvd_vram; diff --git a/drivers/gpu/drm/nouveau/nouveau_irq.c b/drivers/gpu/drm/nouveau/nouveau_irq.c index cffc9bc..95220dd 100644 --- a/drivers/gpu/drm/nouveau/nouveau_irq.c +++ b/drivers/gpu/drm/nouveau/nouveau_irq.c @@...

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Not 100% sure that this is needed, but BSP/MPEG are in the mask. drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c index 0cb322a..f25fc5f 100644 ---

.... @@ -93,7 +93,7 @@ The PFIFO can be split into roughly 4 pieces: - PFIFO puller: executes the commands, passes them to the proper engine, or to the driver. - PFIFO switcher: ticks out the time slices for the channels and saves / - restores the state of the channel between PFIFO registers and RAMFC + restores the state of the channels between PFIFO registers and RAMFC memory. A channel consists of the following: @@ -133,7 +133,7 @@ is being submitted. See :ref:`nv03-pfifo-dma` for details. NV04 PFIFO greatly enhanced the DMA mode and made it controllable directly through the channe...

...not regs, neither masks */ -#define NV03_FIFO_CMD_JUMP 0x20000000 -#define NV03_FIFO_CMD_JUMP_OFFSET_MASK 0x1ffffffc -#define NV03_FIFO_CMD_REWIND (NV03_FIFO_CMD_JUMP | (0 & NV03_FIFO_CMD_JUMP_OFFSET_MASK)) - -/* RAMFC offsets */ -#define NV04_RAMFC_DMA_PUT 0x00 -#define NV04_RAMFC_DMA_GET 0x04 +// /* Fifo commands. These are not regs, neither masks */ +// #define NV03_FIFO_CMD_JUMP 0x20000000 +// #define N...

--- rnndb/memory/nvc0_pbfb.xml | 37 ++++++++++++++++++++++++++++++++++--- 1 file changed, 34 insertions(+), 3 deletions(-) diff --git a/rnndb/memory/nvc0_pbfb.xml b/rnndb/memory/nvc0_pbfb.xml index 500cea9..e006dbe 100644 --- a/rnndb/memory/nvc0_pbfb.xml +++ b/rnndb/memory/nvc0_pbfb.xml @@ -49,23 +49,54 @@ Most bitfields are unknown. </doc> <bitfield high="7"

https://bugs.freedesktop.org/show_bug.cgi?id=61321 Priority: medium Bug ID: 61321 Keywords: regression Assignee: nouveau at lists.freedesktop.org Summary: [regression][NV4c] System hang while loading gdm on 3.7 kernel (works on 3.6) QA Contact: xorg-team at lists.x.org Severity: major Classification:

From: Thierry Reding <treding at nvidia.com> Hi Ben, these are a couple of patches that are in preparation for adding GV11B support. The fundamental issue that these are trying to solve is that the GV11B is the first Tegra incarnation of the GPU where the aperture really matters. All prior generations would accept any of them. For dGPUs we usually allocate memory in VRAM, so the default

...rmine_amount] RAMIN size: 1024KiB Aug 6 21:11:46 localhost [drm:nv04_instmem_configure_fixed_tables] RAMHT offset=0x10000, size=512 Aug 6 21:11:46 localhost [drm:nv04_instmem_configure_fixed_tables] RAMRO offset=0x11200, size=512 Aug 6 21:11:46 localhost [drm:nv04_instmem_configure_fixed_tables] RAMFC offset=0x20000, size=4096 Aug 6 21:11:46 localhost [drm:nouveau_mem_init] Available VRAM: 130048KiB Aug 6 21:11:46 localhost [drm:nouveau_mem_init] Allocating sg memory for PCI DMA Aug 6 21:11:46 localhost [drm:drm_sg_alloc] drm_sg_alloc Aug 6 21:11:46 localhost [drm:drm_sg_alloc] sg size=16777...