search for: raed

Dear all, i have the attached data called "new" as data.frame. First I have only three columns called Var1, Var2 and Freq and with bind I attached the column test for a color specification (TEST DATA below). With this plot function (require packages lattice) dotplot(reorder(Var1, rep(score, cl.count)) ~ Freq | Var2, data = DATA, origin = 0, type = c("p",

Dear all, i try to plot with ggplot2. Therefor I have an matrix with 3 colums. With cbind I add an additional column called "col". I need this column "col" because in a later step and want to specify here some plot details which I will get from another analysis If I want to plot with this code, I have the problem that the legend is wrong. Blue changed to green and green to

Akira, Thanks you for response. I understand Post-RA schedule make uses of scoreboardHazardRecognizer. But I found mips codes are good enough by default. basically, I can not easily eyeball any bubbles. I don't understand how they can do that without post-RA-sched. pre-ra-scheduler eg. (SelectionDAG/ScheduleDAGRRList.cpp) has little information and they can only schedule node in topology

Hi, Akira, I found you maintain mips MipsSchedule.td. does it correct? in MipsSchedule.td, every InstrItinData only uses one InstrStage. there's no ByPass info out there. are you sure this reflects the real R4xxx/R5xxx processors. why IILoad uses funcition unit ALU? InstrItinData<IILoad , [InstrStage<3, [ALU]>]> for my previous question, I have new input after

> On Jan 16, 2018, at 11:31 PM, Martin J. O'Riordan <MartinO at theheart.ie> wrote: > > Thanks Matthias, > > I have both a pre-RA and a post-RA scheduler, and I had thought that I could track “has RA happened?” by setting a flag in my pre-RA scheduler as it completes - my suspicion (which you have confirmed) was that “#vregs == 0” was not a safe assumption. What I

Hi, LLVM, I found LLVM codegen has 3 passes for instruction scheduling: 1) pre-ra sched 2) post-ra sched 3) mi sched. for RISC machines, there are data hazard cases appear only after Register Allocation(RA). for example, $t0 is used immediately after writing(RAW): ld $t0, MEM add $t2, $t0, $0 There may be one or more stall in pipeline. Instruction scheduler can detect this kinds of conflict

Please don't rely on this for checking whether regalloc was run: You can have functions without vregs pre-RA[1]. We don't need or should track state such as pre/post-RA as part of the function. Instead it really is a property of where a pass was scheduled, so the pass should know and not the function. I'd recommend simply creating a pre-RA and a post-RA pass instead of scheduling the

Thanks Matthias, I have both a pre-RA and a post-RA scheduler, and I had thought that I could track “has RA happened?” by setting a flag in my pre-RA scheduler as it completes - my suspicion (which you have confirmed) was that “#vregs == 0” was not a safe assumption. What I cannot be sure of, is what passes execute after my pre-RA scheduler but before RA, and what passes execute after RA but

Hi, Matthias. >From the class hierarchy, ScheduleDAGMILive is also a ScheduleDAGMI. I am wondering if there will be any problem if we use subclass of ScheduleDAGMILive as post-RA scheduler? The best case is ScheduleDAGMILive just waste time on book-keeping register pressure, but I am not sure if we can still do those book-keeping after RA. Talk about post-RA scheduler, I see there is another

Mips invokes the post-RA scheduler only when OptLevel > Aggressive, so you will have to compile with -O3. You can also invoke the MI (pre-RA) scheduler with llc option "-enable-misched". As you have pointed out, the post-isel scheduler is mandatory, and therefore you don't have to give any command line options. Currently, mips has only one generic scheduling itinerary model in

Hi! I've tried to install java plugin as is in http://www.howtoforge.com/installation-guide-centos5.1-desktop-p7 but with no success. All steps seems to go well, with no error messages, but Firefox says that there is no java plugin. Please, tell me what could be wrong? Thanks in advance!! -- Sergio Belkin ----------------------------------------

On Feb 9, 2007, at 7:42 PM, Chris Lattner wrote: > On Fri, 9 Feb 2007, Scott Michel wrote: >> I would have expected four additional patterns, each with the (and >> $rC, $rA) >> variant in it. But I only get the above four. >> >> Is this a bug or a feature? :-) > > This is a feature. They would match the same pattern, so it would > just be >

On Fri, Sep 20, 2013 at 3:30 AM, Liu Xin <navy.xliu at gmail.com> wrote: > Hi, Akira, > > I found you maintain mips MipsSchedule.td. does it correct? in > MipsSchedule.td, every InstrItinData only uses one InstrStage. there's no > ByPass info out there. > are you sure this reflects the real R4xxx/R5xxx processors. > > why IILoad uses funcition unit ALU? >

Hi, >> have not found any easy way to do it yet. For post-RA pass it is >> very easy and supported, but for pre-RA or post-code-selection - it >> is non obvious. > > I suggest a third approach: [snip] > 3. Write a machine function pass that runs before the RA that > translates these instructions into libcalls or other integer ops. > This would lower the f64

Hi All, The description of ScheduleDAGMILive [1] says: ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while updating LiveIntervals and tracking regpressure. Does the live interval and register pressure part of ScheduleDAGMILive mean the subclass of ScheduleDAGMILive is a pre-RA scheduler? I assume the post-RA scheduler no need to take

I've got an instruction that has the following pattern (R32C is the 32-bit register class): (set R32C:$rT, (or (and R32C:$rA, R32C:$rC), (and R32C:$rB, (not R32C:$rC)))) tblgen generates the following variants (I've dropped the R32C for brevity): (or (and $rA, $rC), (and $rB, (not $rC))) # original (or (and $rA, $rC), (and (not $rC), $rB)) (or (and $rB, (not

On Fri, Jan 29, 2016 at 10:22 AM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 1/28/2016 8:11 PM, Rail Shafigulin via llvm-dev wrote: > >> >> Would anyone be able to figure out why this is happening? I can provide >> more code if needed. >> > > The error message should show what types have been inferred so far. > > You

On the other hand this file hasn't changed recently, but I have no way to test this as it uses the LLDB code path, which only runs on OSX. On Mon, Nov 13, 2017 at 3:19 PM Zachary Turner <zturner at google.com> wrote: > I might be missing something, but this doesn't look like me? > > >

We are currently running the post-ra scheduler for x86 with -O3. It is not really clear that it is worth the compile time. X86 scheduling is a mystery that post-ra has not solved. I ran the nightly test suite on x86_64 with LTO enabled and -O3 with and without -disable-post-ra. Code generation is 10% faster overall with -disable-post-ra, and the runtime impact varies from a 17% speedup to a 17

I would like to add a class to the SparseM package. I have a class "matrix.csr" that describes a matrix in compressed sparse row format, now I would like a class matrix.diag.csr that describes such objects when they happen to be diagonal. The idea is that matrix.diag.csr objects should behave (later in life) exactly like matrix.csr objects, the distinction is only needed in order to