Displaying 3 results from an estimated 3 matches for "r4v".
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2007 Mar 27
0
[LLVMdev] Live intervals and aliasing registers problem
...a back end I came across
> the following problem: as soon as I define two sets of registers
> that have a many-to-one mapping the live interval pass appears to
> double-kill the mapped-onto register. I have the following excerpts
> from my RegisterInfo.td.
>
> def V4R0 : R4v<0 , "V4R0 ", []>, DwarfRegNum<0>;
>
> def R0 : Rg<0 , "R0", [V4R0]>, DwarfRegNum<0>;
> def R1 : Rg<1 , "R1", [V4R0]>, DwarfRegNum<1>;
How are R4v and Rg defined?
>
> when trying to compile:
>
> define void...
2007 Mar 25
2
[LLVMdev] Live intervals and aliasing registers problem
...g to add vector registers to a back end I came across
the following problem: as soon as I define two sets of registers that
have a many-to-one mapping the live interval pass appears to double-
kill the mapped-onto register. I have the following excerpts from my
RegisterInfo.td.
def V4R0 : R4v<0 , "V4R0 ", []>, DwarfRegNum<0>;
def R0 : Rg<0 , "R0", [V4R0]>, DwarfRegNum<0>;
def R1 : Rg<1 , "R1", [V4R0]>, DwarfRegNum<1>;
when trying to compile:
define void @_Z3fooii(i32 %a, i32 %b) {
entry:
%retval = select i...
2007 Apr 03
2
[LLVMdev] Live intervals and aliasing registers problem
...> across the following problem: as soon as I define two sets of
>> registers that have a many-to-one mapping the live interval pass
>> appears to double-kill the mapped-onto register. I have the
>> following excerpts from my RegisterInfo.td.
>>
>> def V4R0 : R4v<0 , "V4R0 ", []>, DwarfRegNum<0>;
>>
>> def R0 : Rg<0 , "R0", [V4R0]>, DwarfRegNum<0>;
>> def R1 : Rg<1 , "R1", [V4R0]>, DwarfRegNum<1>;
>
> How are R4v and Rg defined?
class Rg<bits<6> num, stri...